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參數(shù)資料
| 型號： | PXA255 |
| 廠商： | Intel Corp. |
| 英文描述： | PXA255 Processor |
| 中文描述： | PXA255處理器 |
| 文件頁數(shù)： | 34/40頁 |
| 文件大?。?/td> | 1191K |
| 代理商： | PXA255 |
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Electrical Specifications
34
Intel PXA255 Processor
Electrical, Mechanical, and Thermal Specification
Figure 6. Sleep Mode Timing
Table 18. Sleep Mode Timing Specifications
Symbol
Description
Min
Typical
Max
Units
tA_GP[x}
Assert time of GPIO wake-up source
(x=[15:0])
91.6
—
—
μ
s
tD_PWR_F
Delay from nRESET_OUT asserted to
PWR_EN de-asserted
61
—
91.6
μ
s
tD_PWR_R
Delay between GP[x] asserted to
PWR_EN asserted
30.5
—
122.1
μ
s
tDSM_VCC
Delay between PWR_EN asserted and
VCC stable
—
10
ms
tD_FAULT
Delay between PWR_EN asserted and
nVDD_FAULT de-asserted
—
10
ms
tDSM_OUT
Delay between PWR_EN asserted and
nRESET_OUT de-asserted, OPDE set
28.0
—
28.5
ms
tDSM_OUT_F
Delay between PWR_EN asserted and
nRESET_OUT de-asserted, FWAKE set
—
—
650
μ
s
tDSM_OUT_O
Delay between PWR_EN asserted and
nRESET_OUT de-asserted, OPDE
clear
10.35
—
10.5
ms
t
DSM_NCS0
Delay between nReset_Out de-asserted
and nCS0 asserted
180.84
—
332
ns
NOTE:
For the parameter t
DSM_VCC
, VCC refers to the VCC supply internal to the processor. The internal
VCC regulator must be stable within the stated maximum for the processor to function correctly.
Factors such as external voltage regulator ramp time and bulk capacitance will affect the ramp time of
the internal regulator and must be taken into account when designing the system.
GP[x]
PWR_EN
VCC
nVDD_FAULT
nRESET_OUT
t
DSM_OUT
Note: nBATT_FAULT must be high or the PXA255 processor
will not exit sleep mode.
t
A_GP[x]
t
D_PWR_R
t
D_PWR_F
t
D_F A UL T
t
DSM_VCC
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