參數(shù)資料
型號: PSD934F2-90M
廠商: 意法半導體
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù): 50/94頁
文件大小: 476K
代理商: PSD934F2-90M
PSD9XX Family
Preliminary Information
46
The
PSD9XX
Functional
Blocks
(cont.)
9.4.2.4 Address In Mode
For microcontrollers that have more than 16 address lines, the higher addresses can be
connected to Port A, B, C, and D. The address input can be latched by the address strobe
(ALE/AS). Any input that is included in the DPLD equations for the Main Flash, Secondary
Flash, or SRAM is considered to be an address input.
9.4.2.5 Data Port Mode
Port A can be used as a data bus port for a microcontroller with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the microcontroller. The
general I/O functions are disabled in Port A if the port is configured as a Data Port.
9.4.2.6 JTAG ISP
Port C is JTAG compliant, and can be used for In-System Programming (ISP). For more
information on the JTAG Port, refer to section 9.6.
9.4.2.3 Address Out Mode
For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used
to drive latched addresses onto the port pins. These port pins can, in turn, drive external
devices. Either the output enable or the corresponding bits of both the Direction Register
and Control Register must be set to a ‘1’ for pins to use Address Out Mode. This must be
done by the MCU at run-time. See Table 22 for the address output pin assignments on
Ports A and B for various MCUs.
For non-multiplexed 8 bit bus mode, address lines A[7:0] are available to Port B in
Address Out Mode.
Note:
Do not drive address lines with Address Out Mode to an external memory device if
it is intended for the MCU to boot from the external device. The MCU must first boot from
PSD memory so the Direction and Control register bits can be set.
Microcontroller
Port A (3:0)
Port A (7:4)
Port B (3:0)
Port B (7:4)
8051XA (8-Bit)
80C251
(Page Mode)
N/A*
N/A
Address (7:4)
N/A
Address (11:8)
Address (11:8)
N/A
Address (15:12)
All Other
8-Bit Multiplexed
8-Bit
Non-Multiplexed Bus
Address (3:0)
Address (7:4)
Address (3:0)
Address (7:4)
N/A
N/A
Address [3:0]
Address [7:4]
Table 22. I/OPort Latched Address Output Assignments
N/A = Not Applicable.
相關(guān)PDF資料
PDF描述
PSD934F2-90MI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-70J Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-70M Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-90JI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-90MI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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