參數(shù)資料
型號(hào): PSD934F2-90M
廠商: 意法半導(dǎo)體
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù): 12/94頁(yè)
文件大?。?/td> 476K
代理商: PSD934F2-90M
PSD9XX Family
Preliminary Information
8
5.7 In-System Programming
Using the JTAG signals on Port C, the entire PSD9XX device can be programmed or
erased without the use of the microcontroller (ISP). The main Flash memory can also be
programmed in-system by the microcontroller executing the programming algorithms out of
the Secondary Flash memory, or SRAM (IAP). The Secondary Flash memory can be
programmed the same way by executing out of the main Flash memory. The PLD logic
or other PSD9XX configuration can be programmed through the JTAG port or a device
programmer. Table 4 indicates which programming methods can program different
functional blocks of the PSD9XX.
PSD9XX
Architectural
Overview
(cont.)
Device
Programmer
Functional Block
JTAG-ISP
IAP
Main Flash Memory
Yes
Yes
Yes
Secondary Flash Memory
Yes
Yes
Yes
PLD Array (DPLD and GPLD)
Yes
Yes
No
PSD Configuration
Yes
Yes
No
Table 4. Methods of Programming Different Functional Blocks of the PSD9XX
5.8 Power Management Unit
The Power Management Unit (PMU) in the PSD9XX gives the user control of the power
consumption on selected functional blocks based on system requirements. The PMU
includes an Automatic Power Down unit (APD) that will turn off device functions due to
microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce power
consumption.
The PSD9XX also has some bits that are configured at run-time by the MCU to reduce
power consumption of the PLD. The turbo bit in the PMMR0 register can be turned off and
the PLD will latch its outputs and go to sleep until the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set by the MCU to block signals from
entering the PLD to reduce power consumption. See section 9.5.
相關(guān)PDF資料
PDF描述
PSD934F2-90MI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-70J Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-70M Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-90JI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-90MI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD934F2V-15J 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 3.3V 2M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD934F2V-15M 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD834F2V-15M RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD935G2-90U 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 TQFP-80 5V 4M 90N RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD935G2V-90U 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD835G2V-90U RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD954F2-90J 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD854F2-90J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24