參數(shù)資料
型號(hào)： PSD934F2-70M
廠商： 意法半導(dǎo)體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù)： 37/94頁(yè)
文件大?。?/td> 476K
代理商： PSD934F2-70M
Preliminary Information
PSD9XX Family
33
9.2.1 Decode PLD (DPLD)
The DPLD, shown in Figure 10, is used for decoding the address for internal PSD
components. The DPLD can generate the following chip selects:
8 sector selects for the main Flash memory (three product terms each)
4 sector selects for the Secondary Flash memory (three product terms each)
1 internal SRAM select (two product terms)
1 internal CSIOP select (select PSD registers, one product term)
Inputs to the DPLD chip selects may include address inputs, Page Register inputs and
other user defined external inputs from Ports A, B, C or D.
9.2.2 General Purpose PLD (GPLD)
The General Purpose PLD implements user defined system combinatorial logic function
or chip selects for external devices. Figure 11 shows how the GPLD is connected to the
I/O Ports. The GPLD has 19 outputs and each are routed to a port pin. The port pin can
also be configured as input tot eh GPLD. When it is not used as GPLD output or input, the
pin can be configured to perform other I/O functions.
The GPLD outputs are identical except in the number of available product terms for logic
implementation. Select the pin that can best meet the product term requirement of your
logic function or chip selects. The outputs can be configured as active high or low outputs.
Table 16 shows the number of product terms that are assigned to the PLD outputs on the
I/O Ports. When PSD9XX is connected to a MCU with non-multiplexed bus, Port A will be
configured as the Data Port and the GPLD outputs will not be available.
The
PSD9XX
Functional
Blocks
(cont.)
GPLD Output on Port Pin
Number of Product Terms
Port A, pins PA0-3
Port A, pins PA4-7
Port B, pins PB0-3
Port B, pins PB4-7
Port D, pins PD0-2
3
9
4
7
1
Table 16. GPLD Output Product Term
相關(guān)PDF資料
PDF描述
PSD934F2-90J Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD934F2-90JI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD934F2-90M Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD934F2-90MI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD954F2-70J Flash In-System Programmable ISP Peripherals For 8-bit MCUs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD934F290J 制造商:WSI 功能描述:
PSD934F2-90J 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PLCC-52 5V 2M 90NS RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD934F2-90M 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5V 2M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD934F2V-15J 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 3.3V 2M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD934F2V-15M 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 U 511-PSD834F2V-15M RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
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