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參數(shù)資料
型號(hào)： PPC5606BCLU64
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 40/112頁(yè)
文件大小： 0K
描述： MCU 32BIT 1M 64MHZ
標(biāo)準(zhǔn)包裝： 40
系列： MPC56xx Qorivva
核心處理器： e200z0h
芯體尺寸： 32-位
速度： 64MHz
連通性： CAN，I²C，LIN，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 149
程序存儲(chǔ)器容量： 1MB（1M x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 4K x 16
RAM 容量： 80K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 29x10b，5x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 176-LQFP
包裝： 托盤
Package pinouts and signal descriptions
MPC5607B Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
33
3.8
Nexus 2+ pins
In the 208 MAPBGA package, eight additional debug pins are available (see Table 6).
1 Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module.
PCR.PA = 00
AF0; PCR.PA = 01 AF1; PCR.PA = 10 AF2; PCR.PA = 11 AF2. This is intended to
select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of
the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is
reported as “—”.
2 Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by
setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.
3 The RESET configuration applies during and after reset.
4 208 MAPBGA available only as development package for Nexus2+
5 All WKPU pins also support external interrupt capability. See the WKPU chapter for further details.
6 NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
7 “Not applicable” because these functions are available only while the device is booting. Refer to the BAM
information for details.
8 Value of PCR.IBE bit must be 0
9 This wakeup input cannot be used to exit STANDBY mode.
10 Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
It is up to the user to configure these pins as GPIO when needed.
11 PC[1] is a fast/medium pad but is in medium configuration by default. This pad is in Alternate Function 2 mode after
reset which has TDO functionality. The reset value of PCR.OBE is ‘1’, but this setting has no impact as long as this
pad stays in AF2 mode. After configuring this pad as GPIO (PCR.PA = 0), output buffer is enabled as reset value
of PCR.OBE = 1.
12 Not available in 100 LQFP package
Table 6. Nexus 2+ pin descriptions
Port pin
Function
I/O
direction
Pad type
Function
after reset
Pin number
100
LQFP
144
LQFP
208 MAP
BGA1
1 208 MAPBGA available only as development package for Nexus2+
MCKO
Message clock out
O
F
—
T4
MDO0
Message data out 0
O
M
—
H15
MDO1
Message data out 1
O
M
—
H16
MDO2
Message data out 2
O
M
—
H14
MDO3
Message data out 3
O
M
—
H13
EVTI
Event in
I
M
Pull-up
—
K1
EVTO
Event out
O
M
—
L4
MSEO
Message start/end out
O
M
—
G16
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