參數(shù)資料
型號(hào)： PPC8309VMAGDCA
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 1/2頁(yè)
文件大小： 0K
描述： MPU POWERQUICC II PRO 489-MAP
標(biāo)準(zhǔn)包裝： 84
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
封裝/外殼： 489-LFBGA
供應(yīng)商設(shè)備封裝： 489-PBGA（19x19）
包裝： 托盤
Integrated Communications Processors
MPC8309 PowerQUICC II Pro Processor
Overview
The MPC8309 processor is part of the entry
level MPC830x communications portfolio based
on the e300 core architecture. It addresses
the requirements of networking applications,
including I/O cards for low-end base stations,
low-end Ethernet switches, residential
gateways, modem/routers, industrial control,
factory automation and test and measurement
applications. The MPC830x portfolio extends
current PowerQUICC processor offerings,
delivering an impressive 1.99 DMIPS/MHz
in CPU performance, additional functionality
and faster interfaces while maintaining
code compatibility with PowerQUICC I
and PowerQUICC II processors. MPC830x
processors also provide sub-$10, low power
consumption, a compact board footprint and a
time to market advantage through cost-effective
evaluation kits with optimized BSP and drivers.
Core Complex
The MPC8309 incorporates the e300c3
(MPC603e-based) core, built on Power
Architecture technology, which includes 16 KB
of L1 instruction and data caches, dual integer
units and on-chip memory management units
(MMUs).
QUICC Engine Technology
A communications complex based on
QUICC Engine technology forms the heart
of the networking capability of the MPC830x
portfolio. The QUICC Engine block contains
several peripheral controllers and a 32-bit
RISC controller. Protocol support is provided
by the main workhorses of the device—the
unified communication controllers (UCCs).
Each of the five UCCs can support a variety
of communication protocols, including 10/100
Mbps Ethernet and high-level data link control
(HDLC). Two of the UCCs can also support
IEEE 1588 version-2 time stamping.
System Interface Unit
The MPC8309 processor also includes a 16/32-
bit double data rate (DDR2) memory controller
with ECC support, 4 x CAN, 4 x UARTs,
High-Speed USB 2.0 controller, enhanced
SDHC controller, a 32-bit peripheral
component interconnect (PCI) controller,
a 16-bit local bus and two direct memory
access controllers (DMAC).
In summary, the MPC8309 provides users
with a highly integrated, fully programmable
communications processor helping to ensure
that a cost-effective system solution can be
quickly developed while offering the flexibility
to accommodate new standards and evolving
system requirements.
MPC8309 Features
Excellentperformance,low-power,sub-$10
communications processor
Thee300core,builtonPowerArchitecture
technology, with dual integer units enables
more efficient operations to be conducted
in parallel, resulting in a significant
performance improvement
Thesingle-RISCQUICCEngine
communications module offers a future-
proof solution for next-generation designs
by supporting programmable protocol
termination and network interface
termination to meet evolving
protocol standards
DDR2memorycontroller—one16/32-bit
interface at up to 333 MHz with
ECC support
Peripheralinterfacessuchas32-bit,66
MHz PCI, 16-bit, 66 MHz local bus interface
and High-Speed USB 2.0, 4 x CAN, 4 x
UARTs, enhanced SDHC controller
MPC8309 Block Diagram
16/32-bit DDR2
Controller
e300 Core
Complex
Local Bus
16 KB
D-Cache
16 KB
I-Cache
2 x DUART
I2C, SPI
GPIO, Interrupt
Controller
DMA
PCI
eSDHC
8-bit
4 x
CAN
8-bit
USB
2.0
Or
16-bit GPIO
QUICC Engine
Coherent System Bus
Up to
3 x RMII/MII
or
2 x with
IEEE 1588
2 x HDLC
/TDM
Accelerators
I/O
Core
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