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參數(shù)資料
| 型號： | PL611S-17-XXXUCR |
| 廠商： | PhaseLink Corporation |
| 英文描述： | 1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock |
| 中文描述： | 1.8 - 3.3V的PicoPLLTM千赫到MHz可編程時(shí)鐘 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 234K |
| 代理商： | PL611S-17-XXXUCR |
(Preliminary)
PL611s-17
1.8V-3.3V PicoPLL
TM
KHz to MHz Programmable Clock
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/04/07 Page 7
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION
The following guidelines are to assist you with a performance optimized PCB design:
- Keep all the PCB traces to PL611s-17 as short as
possible, as well as keeping all other traces as far
away from it as possible.
- When a reference input clock is generated from a
crystal (see diagram above), place the PL611s-17
‘FIN’ as close as possible to the ‘Xout’ crystal pin.
This will reduce the cross-talk between the reference
input and the other signals.
- Place the Loop Filter (LF) components as close to
the package pin of PL611s-17 as possible.
- Place a 0.01μF~0.1μF decoupling capacitor
between VDD and GND, on the component side of
the PCB, close to the VDD pin. It is not
recommended to place this component on the
backside of the PCB. Going through vias will reduce
the signal integrity, causing additional jitter and
phase noise.
- It is highly recommended to keep the VDD and
GND traces as short as possible.
- When connecting long traces (> 1 inch) to a CMOS
output, it is important to design the traces as a
transmission line or ‘stripline’, to avoid reflections or
ringing. In this case, the
CMOS output needs to be matched to the trace
impedance. Usually ‘striplines’ are designed for
50 impedance and CMOS outputs usually have
lower than 50 impedance so matching can be
achieved by adding a resistor in series with the
CMOS output pin to the ‘stripline’ trace.
- Please contact PhaseLink for the application note
on how to design outputs driving long traces or the
Gerber files for the PL611s-17 layout.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PL611S-17-XXXUI | 1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock |
| PLA17BN1522R0B2M | EMI Suppression Filters for AC Power Lines |
| PLA10AS1522R0P2M | EMI Suppression Filters for AC Power Lines |
| PLA10AS1522R0R2B | EMI Suppression Filters for AC Power Lines |
| PLA10AS1522R0R2M | EMI Suppression Filters for AC Power Lines |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PL611S-17-XXXUC-R | 制造商:PLL 制造商全稱:PLL 功能描述:1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock |
| PL611S-17-XXXUI | 制造商:PLL 制造商全稱:PLL 功能描述:1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock |
| PL611S-17-XXXUIR | 制造商:PLL 制造商全稱:PLL 功能描述:1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock |
| PL611S-18 | 制造商:PLL 制造商全稱:PLL 功能描述:0.5kHz-125MHz MHz to KHz Programmable ClockTM |
| PL611S-18-XXXGC | 制造商:PLL 制造商全稱:PLL 功能描述:0.5kHz-125MHz MHz to KHz Programmable ClockTM |
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