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參數(shù)資料
| 型號(hào)： | PL611S-17-XXXUCR |
| 廠商： | PhaseLink Corporation |
| 英文描述： | 1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock |
| 中文描述： | 1.8 - 3.3V的PicoPLLTM千赫到MHz可編程時(shí)鐘 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大小： | 234K |
| 代理商： | PL611S-17-XXXUCR |
(Preliminary)
PL611s-17
1.8V-3.3V PicoPLL
TM
KHz to MHz Programmable Clock
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/04/07 Page 5
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
V
DD
-0.5
7
V
Input Voltage Range
V
I
-0.5
V
DD
+0.5
V
Output Voltage Range
V
O
-0.5
V
DD
+0.5
V
Soldering Temperature (Green package)
260
°
C
Data Retention @ 85
°
C
10
Year
Storage Temperature
T
S
-65
150
°
C
Ambient Operating Temperature*
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
-40
85
°
C
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
@ V
DD
=3.3V
200
@ V
DD
=2.5V
166
Input (FIN) Frequency
@ V
DD
=1.8V
10KHz
133
MHz
Input (FIN) Signal Amplitude
Internally AC/DC coupled (High Frequency)
0.9
V
DD
Vpp
Input (FIN) Signal Amplitude
Internally AC/DC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
0.1
V
DD
V
pp
@ V
DD
=3.3V
125
@ V
DD
=2.5V
90
Output Frequency
@ V
DD
=1.8V
65
MHz
Settling Time
At power-up (after V
DD
increases over 1.62V)
2
ms
OE Function; Ta=25o C, 15pF Load
10
ns
Output Enable Time
PDB Function; Ta=25o C, 15pF Load
2
ms
Output Rise Time
15pF Load, 10/90% V
DD
, High Drive, 3.3V
1.2
1.7
ns
Output Fall Time
15pF Load, 90/10% V
DD
, High Drive, 3.3V
1.2
1.7
ns
Duty Cycle
V
DD
/2
45
50
55
%
Period Jitter, Pk-to-Pk*
(measured from 10,000 samples)
* Note: Jitter performance depends on the programming parameters.
With capacitive decoupling between V
DD
and
GND.
70
ps
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PL611S-17-XXXUC-R | 制造商:PLL 制造商全稱:PLL 功能描述:1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock |
| PL611S-17-XXXUI | 制造商:PLL 制造商全稱:PLL 功能描述:1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock |
| PL611S-17-XXXUIR | 制造商:PLL 制造商全稱:PLL 功能描述:1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock |
| PL611S-18 | 制造商:PLL 制造商全稱:PLL 功能描述:0.5kHz-125MHz MHz to KHz Programmable ClockTM |
| PL611S-18-XXXGC | 制造商:PLL 制造商全稱:PLL 功能描述:0.5kHz-125MHz MHz to KHz Programmable ClockTM |
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