- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3862 > PIC18F45J11-I/PT (Microchip Technology)IC PIC MCU FLASH 32KB 44-TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | PIC18F45J11-I/PT |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 180/228頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 32KB 44-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | XLP Deep Sleep Mode PIC18 J Series MCU Overview 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | PIC® XLP™ 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 48MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 32KB（16K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 3.8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.15 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 13x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 657 (CN2011-ZH PDF) |
| 配用： | AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)當(dāng)前第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)
2011 Microchip Technology Inc.
DS39932D-page 55
PIC18F46J11 FAMILY
On devices that support it, the Deep Sleep mode is
entered by:
Setting the REGSLP (WDTCON<7>) bit (the
default state on device Reset)
Clearing the IDLEN bit (the default state on device
Reset)
Setting the DSEN bit (DSCONH<7>)
Executing the SLEEP instruction immediately after
setting DSEN (no delay in between)
In order to minimize the possibility of inadvertently enter-
ing Deep Sleep, the DSEN bit is cleared in hardware
two instruction cycles after having been set. Therefore,
in order to enter Deep Sleep, the SLEEP instruction must
be executed in the immediate instruction cycle after set-
ting DSEN. If DSEN is not set when Sleep is executed,
the device will enter conventional Sleep mode instead.
During Deep Sleep, the core logic circuitry of the
microcontroller is powered down to reduce leakage
current. Therefore, most peripherals and functions of
the microcontroller become unavailable during Deep
Sleep. However, a few specific peripherals and func-
tions are powered directly from the VDD supply rail of
the microcontroller, and therefore, can continue to
function in Deep Sleep.
Entering Deep Sleep mode clears the DSWAKEL regis-
ter. However, if the Real-Time Clock and Calendar
(RTCC) is enabled prior to entering Deep Sleep, it will
continue to operate uninterrupted.
The device has dedicated low-power Brown-out Reset
(DSBOR) and Watchdog Timer Reset (DSWDT) for
monitoring voltage and time-out events in Deep Sleep.
The DSBOR and DSWDT are independent of the stan-
dard BOR and WDT used with other power-managed
modes (Run, Idle and Sleep).
When a wake event occurs in Deep Sleep mode (by
MCLR Reset, RTCC alarm, INT0 interrupt, ULPWU or
DSWDT), the device will exit Deep Sleep mode and
perform a Power-on Reset (POR). When the device is
released from Reset, code execution will resume at the
device’s Reset vector.
4.6.1
PREPARING FOR DEEP SLEEP
Because VDDCORE could fall below the SRAM retention
voltage while in Deep Sleep mode, SRAM data could
be lost in Deep Sleep. Exiting Deep Sleep mode
causes a POR; as a result, most Special Function
Registers will reset to their default POR values.
Applications needing to save a small amount of data
throughout a Deep Sleep cycle can save the data to the
general purpose DSGPR0 and DSGPR1 registers. The
contents of these registers are preserved while the
device is in Deep Sleep, and will remain valid throughout
an entire Deep Sleep entry and wake-up sequence.
4.6.2
I/O PINS DURING DEEP SLEEP
During Deep Sleep, the general purpose I/O pins will
retain their previous states.
Pins that are configured as inputs (TRIS bit set) prior to
entry into Deep Sleep will remain high-impedance
during Deep Sleep.
Pins that are configured as outputs (TRIS bit clear)
prior to entry into Deep Sleep will remain as output pins
during Deep Sleep. While in this mode, they will drive
the output level determined by their corresponding LAT
bit at the time of entry into Deep Sleep.
When the device wakes back up, the I/O pin behavior
depends on the type of wake-up source.
If the device wakes back up by an RTCC alarm, INT0
interrupt, DSWDT or ULPWU event, all I/O pins will
continue to maintain their previous states, even after the
device has finished the POR sequence and is executing
application code again. Pins configured as inputs during
Deep Sleep will remain high-impedance, and pins con-
figured as outputs will continue to drive their previous
value.
After waking up, the TRIS and LAT registers will be
reset, but the I/O pins will still maintain their previous
states. If firmware modifies the TRIS and LAT values for
the I/O pins, they will not immediately go to the newly
configured states. Once the firmware clears the
RELEASE bit (DSCONL<0>), the I/O pins will be
“released”. This causes the I/O pins to take the states
configured by their respective TRIS and LAT bit values.
If the Deep Sleep BOR (DSBOR) circuit is enabled, and
VDD drops below the DSBOR and VDD rail POR thresh-
olds, the I/O pins will be immediately released similar to
clearing the RELEASE bit. All previous state informa-
tion will be lost, including the general purpose DSGPR0
and DSGPR1 contents. See Section 4.6.5 “Deep
for additional
details about this scenario.
If a MCLR Reset event occurs during Deep Sleep, the I/O
pins will also be released automatically, but in this case,
the DSGPR0 and DSGPR1 contents will remain valid.
In all other Deep Sleep wake-up cases, application
firmware needs to clear the RELEASE bit in order to
reconfigure the I/O pins.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PIC24HJ12GP201-I/SO | IC PIC MCU FLASH 12KB 18SOIC |
| DSPIC33FJ06GS102-I/SO | IC DSPIC MCU/DSP 6K 28-SOIC |
| PIC32MX220F032D-I/PT | IC MCU 32BIT 32KB FLASH 44TQFP |
| SFW9R-2STE1 | SFW9R-2STE1-FFC/FPC CONN |
| SFW5R-1STE1 | SFW5R-1STE1-FFC/FPC CONN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PIC18F45J11T-I/ML | 功能描述:8位微控制器 -MCU 32KB Flash 4KBRAM 12MIPS nanoWatt RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F45J11T-I/PT | 功能描述:8位微控制器 -MCU 32KB Flash 4KBRAM 12MIPS nanoWatt RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F45J50-I/ML | 功能描述:8位微控制器 -MCU Full Spd USB 32KB 4KBRAM nanoWatt RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F45J50-I/PT | 功能描述:8位微控制器 -MCU Full Spd USB 32KB 4KBRAM nanoWatt RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F45J50T-I/ML | 功能描述:8位微控制器 -MCU Full Spd USB 32KB 4KBRAM nanoWatt RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。