參數(shù)資料
型號(hào): PIC18F45J11-I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 160/228頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 32KB 44-TQFP
產(chǎn)品培訓(xùn)模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 160
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 657 (CN2011-ZH PDF)
配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
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2011 Microchip Technology Inc.
DS39932D-page 37
PIC18F46J11 FAMILY
3.0
OSCILLATOR
CONFIGURATIONS
3.1
Overview
Devices in the PIC18F46J11 family incorporate a
different oscillator and microcontroller clock system
than general purpose PIC18F devices.
The PIC18F46J11 family has additional prescalers and
postscalers, which have been added to accommodate
a wide range of oscillator frequencies. Figure 3-1
provides an overview of the oscillator structure.
Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator block
and clock switching, remain the same. They are
discussed later in this chapter.
3.1.1
OSCILLATOR CONTROL
The operation of the oscillator in PIC18F46J11 family
devices is controlled through three Configuration regis-
ters and two control registers. Configuration registers,
CONFIG1L, CONFIG1H and CONFIG2L, select the
oscillator mode, PLL prescaler and CPU divider
options. As Configuration bits, these are set when the
device is programmed and left in that configuration until
the device is reprogrammed.
The OSCCON register (Register 3-2) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
The OSCTUNE register (Register 3-1) is used to trim the
INTOSC frequency source and select the low-frequency
clock source that drives several special features. The
OSCTUNE register is also used to activate or disable the
Phase Locked Loop (PLL). Its use is described in
.
3.2
Oscillator Types
PIC18F46J11 family devices can be operated in eight
distinct oscillator modes. Users can program the
FOSC<2:0> Configuration bits to select one of the
modes listed in Table 3-1. For oscillator modes which
produce a clock output (CLKO) on pin RA6, the output
frequency will be one fourth of the peripheral clock
frequency. The clock output stops when in Sleep mode,
but will continue during Idle mode (see Figure 3-1).
TABLE 3-1:
OSCILLATOR MODES
Mode
Description
ECPLL
External Clock Input mode, the PLL can
be enabled or disabled in software,
CLKO on RA6, apply external clock
signal to RA7.
EC
External Clock Input mode, the PLL is
always disabled, CLKO on RA6, apply
external clock signal to RA7.
HSPLL
High-Speed Crystal/Resonator mode,
PLL can be enabled or disabled in
software, crystal/resonator connected
between RA6 and RA7.
HS
High-Speed Crystal/Resonator mode,
PLL always disabled, crystal/resonator
connected between RA6 and RA7.
INTOSCPLLO Internal Oscillator mode, PLL can be
enabled or disabled in software, CLKO
on RA6, port function on RA7, the
internal oscillator block is used to derive
both the primary clock source and the
postscaled internal clock.
INTOSCPLL Internal Oscillator mode, PLL can be
enabled or disabled in software, port
function on RA6 and RA7, the internal
oscillator block is used to derive both the
primary clock source and the postscaled
internal clock.
INTOSCO
Internal Oscillator mode, PLL is always
disabled, CLKO on RA6, port function on
RA7, the output of the INTOSC
postscaler serves as both the postscaled
internal clock and the primary clock
source.
INTOSC
Internal Oscillator mode, PLL is always
disabled, port function on RA6 and RA7,
the output of the INTOSC postscaler
serves as both the postscaled internal
clock and the primary clock source.
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