參數(shù)資料
型號(hào): PIC16LC662T-04/L
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 87/136頁
文件大?。?/td> 634K
代理商: PIC16LC662T-04/L
PIC16C64X & PIC16C66X
DS30559A-page 54
Preliminary
1996 Microchip Technology Inc.
8.1
Conguring the Voltage Reference
The Voltage Reference Module can output 16 distinct
voltage levels for each range.
The equations used to calculate the output of the
Voltage Reference are as follows:
If VRR = 1
Then VREF = (VR3:VR0/24) VDD
If VRR = 0
Then VREF = (VDD 1/4) + (VR3:VR0/32) VDD
The settling time of the Voltage Reference must be
considered
when
changing
the
VREF
output
(Table 12-2). Example 8-1 shows an example of how to
congure the Voltage Reference for an output voltage
of 1.25V with VDD = 5.0V.
EXAMPLE 8-1:
VOLTAGE REFERENCE
CONFIGURATION
MOVLW
0x02
; 4 inputs muxed
MOVWF
CMCON
; to 2 comparators
BSF
STATUS,RP0
; Select Bank 1
MOVLW
0x07
; RA3:RA0 to outputs
MOVWF
TRISA
;
MOVLW
0xA6
; enable Vref low
MOVWF
VRCON
; range, VR3:VR0 = 6
BCF
STATUS,RP0
; Select Bank 0
CALL
DELAY_10
s
; 10
s delay
8.2
Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 8-2) keep VREF from approaching VSS or VDD.
The Voltage Reference is VDD derived and therefore,
the VREF output changes with uctuations in VDD. The
absolute accuracy of the Voltage Reference can be
found in Table 12-3.
8.3
Operation During Sleep
When the device wakes up from sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference Module should be disabled.
8.4
Effects of a Reset
A device reset disables the Voltage Reference by clear-
ing
bit
VREN
(VRCON<7>).
This
reset
also
disconnects the reference from the RA2 pin by clearing
bit VROE (VRCON<6>) and selects the high voltage
range by clearing bit VRR (VRCON<5>). The VREF
value select bits, VRCON<3:0>, are also cleared.
8.5
Connection Considerations
The Voltage Reference Module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA<2> bit is set and bit VROE is set. Enabling the
Voltage Reference output onto the RA2 pin with an
input signal present will increase current consumption.
Connecting RA2 as a digital output with VREF enabled
will also increase current consumption.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
VREF.
shows
an
example
buffering
technique.
FIGURE 8-3:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
TABLE 8-1:
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value On
POR,
BOR
Value on
all other
resets
9Fh
VRCON
VREN
VROE
VRR
VR3
VR2
VR1
VR0
000- 0000
1Fh
CMCON
C2OUT
C1OUT
CIS
CM2
CM1
CM0
00-- 0000
85h
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
--11 1111
Note 1: R is dependent upon the Voltage Reference Conguration VRCON<3:0> and VRCON<5>.
VREF output
Voltage
Reference
Output
Impedance
R(1)
Pin RA2
VREF
Module
PIC16C662
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