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參數(shù)資料
| 型號： | PIC16C925/L |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 148/183頁 |
| 文件大?。?/td> | 3233K |
| 代理商： | PIC16C925/L |
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2001 Microchip Technology Inc.
Preliminary
DS39544A-page 65
PIC16C925/926
9.2
I2C Overview
This section provides an overview of the Inter-
ing the operation of the SSP module in I2C mode.
The I2C bus is a two-wire serial interface developed by
the Philips Corporation. The original specification, or
standard mode, was for data transfers of up to 100
Kbps. An enhanced specification, or fast mode is not
supported. This device will communicate with fast
mode devices if attached to the same bus.
The I2C interface employs a comprehensive protocol to
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
which initiates transfer on the bus and generates the
clock signals to permit that transfer, while the other
device(s) acts as the “slave.” All portions of the slave
protocol are implemented in the SSP module’s hard-
ware, except general call support, while portions of the
master protocol need to be addressed in the
PIC16CXXX software. Table 9-2 defines some of the
I2C bus terminology. For additional information on the
I2C interface specification, refer to the Philips docu-
ment #939839340011, “The I2C bus and how to use it”,
which can be obtained from the Philips Corporation.
In the I2C interface protocol, each device has an
address. When a master wishes to initiate a data trans-
fer, it first transmits the address of the device that it
wishes to “talk” to. All devices “l(fā)isten” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read from/write to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data trans-
fer. That is, they can be thought of as operating in either
of these two relations:
Master-transmitter and Slave-receiver
Slave-transmitter and Master-receiver
In both cases, the master generates the clock signal.
The output stages of the clock (SCL) and data (SDA)
lines must have an open drain or open collector, in
order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high
level when no device is pulling the line down. The num-
ber of devices that may be attached to the I2C bus is
limited only by the maximum bus loading specification
of 400 pF.
9.2.1
INITIATING AND TERMINATING
DATA TRANSFER
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP conditions determine the start and stop of data
transmission. The START condition is defined as a
high to low transition of the SDA when the SCL is high.
The STOP condition is defined as a low to high transi-
tion of the SDA when the SCL is high. Figure 9-6 shows
the START and STOP conditions. The master gener-
ates these conditions for starting and terminating data
transfer. Due to the definition of the START and STOP
conditions, when data is being transmitted, the SDA
line can only change state when the SCL line is low.
FIGURE 9-6:
START AND STOP
CONDITIONS
TABLE 9-2:
I2C BUS TERMINOLOGY
SDA
SCL
S
P
START
Condition
Change
of Data
Allowed
Change
of Data
Allowed
STOP
Condition
Term
Description
Transmitter
The device that sends the data to the bus.
Receiver
The device that receives the data from the bus.
Master
The device which initiates the transfer, generates the clock and terminates the transfer.
Slave
The device addressed by a master.
Multi-master
More than one master device in a system. These masters can attempt to control the bus at the
same time without corrupting the message.
Arbitration
Procedure that ensures that only one of the master devices will control the bus. This ensures that
the transfer data does not get corrupted.
Synchronization
Procedure where the clock signals of two or more devices are synchronized.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PIC16C925T-I/L | 功能描述:8位微控制器 -MCU 7KB 176 RAM 52 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C925T-I/PT | 功能描述:8位微控制器 -MCU 7KB 176 RAM 52 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C926/CL | 功能描述:8位微控制器 -MCU 14KB 336 RAM 52 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C926-I/L | 功能描述:8位微控制器 -MCU 14KB 336 RAM 52 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C926-I/L | 制造商:Microchip Technology Inc 功能描述:8BIT CMOS MCU SMD 16C926 PLCC68 |
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