參數(shù)資料
型號： PIC10F202T-I/PG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, RISC MICROCONTROLLER, PDIP8
封裝： 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-8
文件頁數(shù)： 66/88頁
文件大?。?/td> 1127K
代理商： PIC10F202T-I/PG
2004 Microchip Technology Inc.
Preliminary
DS41239A-page 67
PIC10F200/202/204/206
12.1
DC Characteristics: PIC10F200/202/204/206 (Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40
°C ≤ TA ≤ +85°C (industrial)
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
D001
VDD
Supply Voltage
2.0
5.5
V
D002
VDR
RAM Data Retention Voltage(2)
—
1.5*
—
V
Device in Sleep mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
—Vss
—
V
istics” for details
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
V/ms
istics” for details
D010
IDD
Supply Current(3)
—
170
350
TBD
A
FOSC = 4 MHz, VDD = 2.0V
FOSC = 4 MHz, VDD = 5.0V
D020
IPD
Power-down Current(4)
—0.1
TBD
AVDD = 2.0V
D022
IWDT WDT Current(4)
—1.0
TBD
AVDD = 2.0V
D023
ICMP Comparator Current(4)
—15
TBD
AVDD = 2.0V
D024
IVREF Internal Reference Current(4)
—TBD
TBD
AVDD = 2.0V
Legend: TBD = To Be Determined.
*
These parameters are characterized but not tested.
Note 1:
Data in the Typical (“Typ”) column is based on characterization results at 25
°C. This data is for design
guidance only and is not tested.
2:
This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3:
The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, bus rate, internal code execution pattern and temperature also have an impact on the current
consumption.
a) The test conditions for all IDD measurements in active Operation mode are:
All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in Sleep
mode.
4:
Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and
tied to VDD or VSS.
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