參數(shù)資料
型號： PIC10F202T-I/PG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, RISC MICROCONTROLLER, PDIP8
封裝： 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-8
文件頁數(shù)： 53/88頁
文件大?。?/td> 1127K
代理商： PIC10F202T-I/PG
2004 Microchip Technology Inc.
Preliminary
DS41239A-page 55
PIC10F200/202/204/206
DECF
Decrement f
Syntax:
[ label ] DECF f,d
Operands:
0
≤ f ≤ 31
d
∈ [0,1]
Operation:
(f) – 1
→ (dest)
Status Affected:
Z
Description:
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Operands:
0
≤ f ≤ 31
d
∈ [0,1]
Operation:
(f) – 1
→ d; skip if result = 0
Status Affected:
None
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOP is executed
instead making it a two-cycle
instruction.
GOTO
Unconditional Branch
Syntax:
[ label ]
GOTO k
Operands:
0
≤ k ≤ 511
Operation:
k
→ PC<8:0>;
Status<6:5>
→ PC<10:9>
Status Affected:
None
Description:
GOTO
is an unconditional branch.
The 9-bit immediate value is
loaded into PC bits <8:0>. The
upper bits of PC are loaded from
Status<6:5>. GOTO is a two-cycle
instruction.
INCF
Increment f
Syntax:
[ label ]
INCF f,d
Operands:
0
≤ f ≤ 31
d
∈ [0,1]
Operation:
(f) + 1
→ (dest)
Status Affected:
Z
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ]
INCFSZ f,d
Operands:
0
≤ f ≤ 31
d
∈ [0,1]
Operation:
(f) + 1
→ (dest), skip if result = 0
Status Affected:
None
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, then the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead making it a
two-cycle instruction.
IORLW
Inclusive OR literal with W
Syntax:
[ label ]
IORLW k
Operands:
0
≤ k ≤ 255
Operation:
(W) .OR. (k)
→ (W)
Status Affected:
Z
Description:
The contents of the W register are
OR’ed with the eight bit literal ‘k’.
The result is placed in the W
register.
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