參數(shù)資料
型號: PI90SD1636AFCE
廠商: Pericom
文件頁數(shù): 11/15頁
文件大小: 0K
描述: IC SERDES GIG ETH TXRX 64-LQFP
產(chǎn)品變化通告: Product Discontinuation Notice 11/Feb/2008
標準包裝: 160
類型: 收發(fā)器
規(guī)程: IEEE 802
電源電壓: 3.15 V ~ 3.45 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 管件
5
PS8641
10/14/04
PI90SD1636A
SERDES Gigabit Ethernet Transceiver
Table 2. Pin Description (Continued.)
Name
Pin#
Type
Description
GND_RXT
VCC_RXT
33 46,
37, 42
P
Power and ground pairs for ESD structure.
RX<9>
RX<8>
RX<7>
RX<6>
RX<5>
RX<4>
RX<3>
RX<2>
RX<1>
RX<0>
34
35
36
37
38
39
40
41
43
44
45
TTL_OUT
Received Parallel Data Output. RX<0> is the least significant bit and is
received first. When DIN± lose input data, all RX pins will be held HIGH.
COM_DET
47
TTL_OUT
Comma detect. This pin is active HIGH. When asserted, it indicates the
detection of comma character (0011111XXX). It is active only when EN_CEDT
is enabled.
VCC_RXF
GND_RXF
50
51
P
Power and ground pair for the front-end of the receiver section.
DIN-
52
HS_IN
High-speed serial data input. Serial data input is received when
DIN+
54
EWRAP is disabled.
VCC_RXESD
GND_RXESD
53,55
56
P
Power and ground pair for ESD structure.
VCC_RXA
GND_RXA
57, 59
58
P
Power and ground pair for analog circuits of the receiver section.
VCC_TX_ECL
60
P
Power supply to line driver circuits. Ground supply is from pin 64.
DOUT-
DOUT+
61
62
HS_OUT
High-speed serial data output. These pins are active when EWRAP is disabled
and are held static at logic 1 when EWRAP is enable.
VCC_TX_HS
GND_TX_HS
63
64
P
Power and ground pair for high-speed transmit logic in the parallel-to-serial
section.
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