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參數(shù)資料
| 型號(hào)： | PI90SD1636AFCE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 10/15頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SERDES GIG ETH TXRX 64-LQFP |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 11/Feb/2008 |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類(lèi)型： | 收發(fā)器 |
| 規(guī)程： | IEEE 802 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 管件 |
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4
PS8641
10/14/04
PI90SD1636A
SERDES Gigabit Ethernet Transceiver
Table 2. Pin Description
Name
Pin #
Type
Description
GND_ESD
VCC_ESD
1, 14
5, 10
P
Power and ground pairs for pad ESD structure.
TX<0>
TX<1>
TX<2>
TX<3>
TX<4>
TX<5>
TX<6>
TX<7>
TX<8>
TX<9>
2
3
4
6
7
8
9
11
12
13
TTL_IN 0-bit parallel data input pins. This data should be 10b/8b encoded. The least
significant bit is TX<0> and is transmitted first.
GND_TXA
VCC_TXA
15
18
P
Power and ground pair for TX PLL analog circuits.
NC
16, 17,27,
48, 49
NC
No Connect
EWRAP
19
TTL_IN
Wrap Enable. This pin is active HIGH. When asserted, the high-speed serial data
are internally wrapped from the transmitter serial data output back to the receiver
data input. Also, when asserted, DOUT± are held static at logic 1. When deasserted,
DOUT± and .DIN± are active.
VCC_TXD
GND_TXD
20
21
P
Power and ground pair for TX digital circuits.
TX_CLK
22
TTL_IN
Reference clock and transmit byte clock. This is a 125 MHz system clock supplied
by the host system. On the positive edge of the clock, the input data, TX<9:0>, are
latched into the register. This clock is multiplied by 10 internally, to generate the
transmit serial bit clock.
VCC_RXD
GND_RXD
23 28,
25
P
Power and ground pair for digital circuits in the receiver portion.
EN_CDET
24
TTL_IN
Comma Detect Enable. This pin is active HIGH. When asserted, the internal byte
alignment function is turned on, to allow the clock to synchronize with the comma
character (0011111XXX). When de-asserted, the function is disabled and will not align
the clock and data. In this mode COM_DET is set to LOW.
SIG_DET
26
TTL_
OUT
Signal Detect. This pin is active HIGH. It indicates the loss of input signal on the
high-speed serial inputs, DIN±. SIG_DET is set to LOW when differential inputs are
less than 50 mV.
VCC_RX
GND_RX
29
32
P
Power and ground pair for the clock signal of the receiver portion.
RX_CLK<1>
RX_CLK<0>
30
31
TTL_
OUT
Receiver Byte Clocks. Two 180 degrees out-of-phase 62.5 MHz clock signals that are
recovered by the receiver section. The received bytes are alternately clocked by the
rising edges of these signals. The rising edge of RX_CLK<1> aligns with a comma
character when detected.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PI90SD1636AFCEX | 功能描述:以太網(wǎng) IC 1.25G SERDES Gigabit Ethernet RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| PI90SD1636AFD | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:SERDES Gigabit Ethernet Transceiver |
| PI90SD1636AFDE | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:SERDES Gigabit Ethernet Transceiver |
| PI90SD1636C | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:SERDES Gigabit Ethernet Transceiver |
| PI90SD1636CFC | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:SERDES Gigabit Ethernet Transceiver |
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