5.0Gbps 4-Lane PCIe 2.0 ReDdriver
參數(shù)資料
型號(hào): PI2EQX5864CZFE
廠商: Pericom
文件頁(yè)數(shù): 14/20頁(yè)
文件大?。?/td> 0K
描述: IC PCI-E REDRIVER 56TQFN
標(biāo)準(zhǔn)包裝: 66
系列: ReDriver™
類型: 轉(zhuǎn)接驅(qū)動(dòng)器
Tx/Rx類型: CML
電容 - 輸入: 50pF
電源電壓: 1.15 V ~ 1.25 V
電流 - 電源: 800mA
安裝類型: 表面貼裝
封裝/外殼: 56-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 56-TQFN-EP(5x11)
包裝: 管件
3
PS8934D
07/08/09
PI2EQX5864C
5.0Gbps 4-Lane PCIe 2.0 ReDdriver
with Equalization, Emphasis and I2C Control
DESCRIPTION of OPERATION
Conguration Modes
Device conguration can be performed in two ways depending on the state of the MODE input. MODE determines whether IC
conguration status is from the input pins or via I2C control. When MODE is set high, the conguration input pins set the congura-
tion operating state as stored in conguration registers. While MODE is set high, changes to these control registers are disabled and
the initial condition is protected from any changes to insuring a known operating state. When the MODE pin is low, reprogramming
of these control registers via I2C is allowed. Note that the MODE pin is not latched, and is always active to enable or disable I2C
access.
During initial power-on, the value at the conguration input pins: LB#, RESET#,RXD_A and RXD_B, will be latched to the con-
guration registers as initial startup states.
Equalizer Conguration
The PI2EQX5864C input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) resulting from long signal
traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-frequency signal components. Because either
too little, or too much, signal compensation may be non-optimal eight levels are provided to adjust for any application.
Equalizer conguration can be programmed via I2C when the mode pin is low. Each group of four channels, A and B, has separate
equalization control, and all four channels within the group are assigned the same conguration state. The Equalizer Selection table
below describes the register state and associated operation of the equalizer.
Equalizer Selection
SEL2_[A:B]
SEL1_[A:B]
SEL0_[A:B]
@1.25GHz
@2.5GHz
0
0.5dB
1.2dB
0
1
0.6dB
1.5dB
0
1
0
1.0dB
2.6dB
0
1
1.9dB
4.3dB
1
0
2.8dB
5.8dB
1
0
1
3.6dB
7.1dB
1
0
5.0dB
9.0dB
1
7.7dB
12.3dB
Pin #
Pin Name
Type
Description
24
RESET#
I
RESET# is an active low channel reset input for Channel A0, B0, A1, B1, A2,
B2, A3 and B3 with internal 100K-Ohm pull-up resistor. When low, receiver
detection cycle is reset, and normal detection cycle is carry on after the pin goes
high.
50
RXD_A
I
Receiver detect enable input for Channel A0, A1, A2 and A3 with internal 100K-
Ohm pull-up resistor.
22
RXD_B
I
Receiver detect enable input for Channel B0, B1, B2 and B3 with internal 100K-
Ohm pull-up resistor.
53
SCL
I/O
I2C SCL clock input.
52
SDA
I/O
I2C SDA data input.
55, 56, Center Pad
GND
PWR
Supply Ground
1, 6, 11, 16, 21, 29,
34, 39, 44, 49
VDD
PWR
1.2V Supply Voltage
09-0002
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