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768-Mbit LVQ Family with Asynchronous Static RAM
6
Datasheet
Non-Array Reads
Flash reads which return flash Device Identifier, CFI Query, Protection
Register and Status Register information
Program
An operation to Write data to the flash array
Write
Bus cycle operation at the inputs of the flash die, in which a command
or data are sent to the flash array
Block
Group of cells, bits, bytes or words within the flash memory array that
get erased with one erase instruction
Parameter block
Any 16-Kword flash array block.
Main block
Any 64-Kword flash array block.
Top parameter
Previously referred to as a top-boot device, a device with flash
parameter partition located at the highest physical address of its
memory map for processor system boot up.
Bottom parameter
Previously referred to as a bottom-boot device, a device with flash
parameter partition located at the lowest physical address of its memory
map for processor system boot up.
Bottom-Top parameter
Stacked-CSP device configuration of two flash dies in the same
segment arranged with the parameter partitions located at the lowest
and highest physical address of its memory map.
Partition
A group of flash blocks that shares common status register read state.
Parameter partition
A flash partition containing parameter and main blocks.
Main partition
A flash partition containing only main blocks.
Die
Individual physical flash die used in a stacked-CSP memory subsystem
device
Segment
A section of the SCSP memory subsystem divided for different
operating characteristics. The SCSP memory subsystem has three
segments: a code segment, a data segment, and an xRAM segment.
Code segment
A segment that contains one or two flash memory dies optimized for
fast code or data reads. Each die features multi-partition synchronous
read-while-write or burst read-while-erase capability.
Data segment
A segment contains one or two flash memory dies optimized for large
embedded data. Each die feature single-partition asynchronous read,
write, and erase operations.
xRAM segment
A segment contains one or two xRAM memory dies. The xRAM
combinations could include SRAM, PSRAM, or LPSDRAM.
Subsystem
A stacked memory integration concept made up of multiple memory
dies arranged in Code, Data, and xRAM segments.
Device
An individual flash die or a flash + xRAM SCSP.