參數(shù)資料
型號: PF38F3352LLZDQ0
廠商: INTEL CORP
元件分類: 存儲(chǔ)器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA88
封裝: 11 X 13 MM, SCSP-88
文件頁數(shù): 27/54頁
文件大小: 966K
代理商: PF38F3352LLZDQ0
768-Mbit LVQ Family with Asynchronous Static RAM
Datasheet
33
NOTES:
1. During address transition, at least one of the pins P-CS#, R-WE#, or both of R-UB# and R-LB# pins should
be deasserted.
2. Do not input data to the I/O pins while they are in an output state.
3. In a write cycle, P-Mode and R-OE# should be fixed to high-level.
4. Write operation is done during the overlap time of a low-level P-CS#, R-WE#, R-LB# and/or R-UB#.
Figure 16. Conditions for Calculating the Minimum Value for W14 and W15
Address
R-UB#,R-LB#,
P-CS#
W14, W15
W2
R-WE#
W10
Figure 17. AC Waveform for PSRAM Write Operation
W1
Vih
Vil
W2
W8
Vih
W6
Vil
W5
Vih
W9
Vil
Vih
W3
Vil
Voh
W4
W7
High-Z
Vol
Address
P-CS#
R-UB#,
R-LB#
R-WE#
Data I/O
Valid Data In
Low-Z
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