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參數(shù)資料
| 型號： | PDSP16116MCGGDR |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | 16 X 16 Bit Complex Multiplier |
| 中文描述： | 16 × 16位乘法器復(fù)雜 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 270K |
| 代理商： | PDSP16116MCGGDR |
PDSP16116
2
SYSTEM FEATURES
The PDSP16116 has a number of features tailored for sys-
tem applications.
(
2
1)
3
(
2
1) Trap
In multiply operations using two’s complement fractional no-
tation, the (
2
1)
3
(
2
1) operation forms an invalid result because
1
1 is not representable in the fractional number range. The
PDSP16116 eliminates this problem by trapping the (
2
1)
3
(
2
1)
operation and forcing the multiplier result to become the most
positive representable number.
Complex Conjugation
Many algorithms using complex arithmetic require conjuga-
tion of complex data stream. This operation has traditionally re-
quired an additional ALU to multiply the imaginary component
by -1. The PDSP16116 eliminates this requirement by offering
on-chip complex conjugation of either of the two incoming com-
plex data words with no loss in throughput.
Easy Interfacing
As with all PDSP family members the PDSP16116 has reg-
istered l/O for data and control. Data inputs have independent
clock enables and data outputs have independent three state
output enables.
Signal
XR15:0
Xl15:0
YR15:0
Yl15:0
PR15:0
Pl15:0
CLK
CONX
CONY
ROUND
MBFP
AR15:1 3
Al15:1 3
WTA1:0
WTB1:0
WTOUT1:0
SFTA1:0
SFTR2:0
GWR4:0
OSEL1:0
V
DD
GND
Type
Input
Input
Input
Input
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Input
Input
Power
Power
Description
16-bit input for real X data
16-bit input for imaginary X data
16-bit input for real Y data
16-bit input for imaginary Y data
16-bit output for real P data
16-bit output for imaginary P data
Clock; new data is loaded on rising edge of CLK
Clock, enable X-port input register
Clock, enable Y-port input register
Conjugate X data
Conjugate Y data
Rounds the real and imaginary results
Mode select (BFP/Normal)
Start of BFP operations (see Note 1)
End of pass (See Note 1)
3 MSBs from real part of A-word (See Note 1)
3 MSBs from imaginary part of A-word (See Note 1)
Word tag from A-word
Word tag from B-word/shift control (See Note 2)
Word tag output (See Note 1)
Shift control for A-word / overflow flag (See Note 2)
Shift control for accumulator result (See Note 1)
Global weighting register contents (See Note 1)
Selects the desired output configuration
Output enables
1
5V Supply (See Note 3)
0V Supply (See Note 3)
Normal
mode
configuration
Tie low
Tie low
Tie low
Tie low
Tie low
Tie low
NOTES
1. Used only in BFP mode
2. Performs different functions in BFP/Normal modes
3. All supply pins must be connected
Table 1 Signal descriptions
CEX
CEY
SOBFP
EOPSS
OER, OEI
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PDF描述 |
|---|---|
| PDSP16116A | 16 By 16 Bit Complex Multiplier(16×16位 復(fù)雜乘法器) |
| PDSP16116MC | 16 By 16 Bit Complex Multiplier(16×16位 復(fù)雜乘法器) |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PDSP16256 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Programmable FIR Filter |
| PDSP16256/A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:I/Q Splitter/NCO |
| PDSP16256/BO/AC | 制造商:Microsemi Corporation 功能描述: |
| PDSP16256_98 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Programmable FIR Filter |
| PDSP16256A | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Programmable FIR Filter |
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