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參數(shù)資料
| 型號(hào)： | PDSP16116 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | 16 By 16 Bit Complex Multiplier(16×16位 復(fù)雜乘法器) |
| 中文描述： | 16到16位復(fù)雜乘數(shù)（16 × 16位復(fù)雜乘法器） |
| 文件頁(yè)數(shù)： | 1/17頁(yè) |
| 文件大?。?/td> | 272K |
| 代理商： | PDSP16116 |
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Supersedes October 1997 version, DS3707 - 5.3
DS3707 - 6.0 November 1998
PDSP16116
16 X 16 Bit Complex Multiplier
FEATURES
I
Complex Number (16
1
16)
3
(16
1
16) Multiplication
I
Full 32-bit Result
I
20MHz Clock Rate
I
Block Floating Point FFT Butterfly Support
I
(
2
1)
3
(
2
1) Trap
I
Two’s Complement Fractional Arithmetic
I
TTL Compatible I/O
I
Complex Conjugation
I
2 Cycle Fall Through
I
144-pin PGA or QFP packages
APPLICATIONS
I
Fast Fourier Transforms
I
Digital Filtering
I
Radar and Sonar Processing
I
Instrumentation
I
Image Processing
ORDERING INFORMATION
PDSP16116/MC/GC1R
PDSP16116A B0 AC
PDSP16116A A0 AC
PDSP16116A/IG/GC1R
PDSP16116A/MC/GC1R
20MHz MIL-883 screened
PDSP16116B B0 AC
PDSP16116D IG/GC1R
10MHz MIL-883 screened
20MHz Industrial
20MHz Military
20MHz Industrial
25MHz Industrial
31.5MHz Industrial
ASSOCIATED PRODUCTS
PDSP16318/A
Complex Accumulator
PDSP16112/A
(16
1
16)
3
(12
1
12) Complex Multiplier
PDSP16330/A
Pythagoras Processor
PDSP1601/A
ALU and Barrel Shifter
PDSP16350
Precision Digital Modulator
PDSP16256
Programmable FIR Filter
PDSP16510A
Single Chip FFT Processor
Fig. 1 Simplified block diagram
PR15:0
ADD/SUB
REG
MULT
REG
REG
MULT
REG
REG
MULT
REG
REG
MULT
REG
ADD/SUB
SHIFT
REG
SHIFT
REG
PI15:0
XR15:0
XI15:0
YR15:0
YI15:0
The PDSP16116 contains four 16
3
16 array multipliers, two
32-bit adder/subtractors and all the control logic required to sup-
port Block Floating Point Arithmetic as used in FFT applications.
The PDSP16116A variant will multiply two complex (16
1
16)
bit words every 50ns and can be configured to output the com-
plete complex (32
1
32) bit result within a single cycle. The data
format is fractional two’s complement.
In combination with a PDSP16318A, the PDSP16116A forms
a two-chip 20MHz complex multiplier accumulator with 20-bit
accumulator registers and output shifters. The PDSP16116A in
combination with two PDSP16318As and two PDSP1601As
forms a complete 20MHz Radix 2 DIT FFT butterfly solution
which fully supports block floating point arithmetic. The
PDSP16116 has an extremely high throughput that is suited to
recursive algorithms as all calculations are performed with a
single pipeline delay (two cycle fall-through).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDSP16256C0 | Programmable FIR Filter |
| PDSP16256GC1R | Programmable FIR Filter |
| PDSP16256 | Programmable FIR Filter(可編程快速脈沖響應(yīng)（FIR）濾波器) |
| PDSP16256A | Programmable FIR Filter(可編程快速脈沖響應(yīng)（FIR）濾波器) |
| PDSP16256 | Programmable FIR Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDSP16116A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:16 by 16 Bit Complex Multiplier |
| PDSP16116A0AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
| PDSP16116AA0AC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:16 X 16 Bit Complex Multiplier |
| PDSP16116AA0GG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier |
| PDSP16116AB0AC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:16 X 16 Bit Complex Multiplier |
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