參數(shù)資料
型號(hào): PDSP16116
廠商: Mitel Networks Corporation
英文描述: 16 By 16 Bit Complex Multiplier(16×16位 復(fù)雜乘法器)
中文描述: 16到16位復(fù)雜乘數(shù)(16 × 16位復(fù)雜乘法器)
文件頁(yè)數(shù): 13/17頁(yè)
文件大?。?/td> 272K
代理商: PDSP16116
PDSP16116
13
ELECTRICAL CHARACTERISTICS
The Electrical Characteristics are guaranteed over the following range of operating conditions, unless otherwise stated:
V
DD
=
1
5V
±
10%, GND = 0V, T
AMB
(Industrial) =
2
40
°
C to
1
85
°
C, T
AMB
(Military) =
2
55
°
C to
1
125
°
C
Static Characteristics
Min.
Typ.
Max.
Output high voltage
Output low voltage
Input high voltage
Input high voltage
Input low voltage
Input leakage current
Input capacitance
Output leakage current
Output short circuit current
10
-
0·4
-
-
0·8
1
10
1
50
300
2·4
-
3·0
2·2
-
2
10
2
50
10
V
OH
V
OL
V
IH
V
IH
V
IL
I
IN
C
IN
I
OZ
I
OS
I
OH
= 8mA
I
OL
=
2
8mA
CLK input only
All other inputs
GND < V
IN
< V
DD
GND < V
OUT
< V
DD
V
DD
=
1
5·5V
V
V
V
V
V
μ
A
pF
μ
A
mA
Units
Value
Conditions
Characteristic
Symbol
P ports setup time
WTOUT1:0 setup time
GWR4:0 setup time
SFTA1:0 setup time
SFTR2:0 setup time
CEX
or
CEY
setup time
CEX
or
CEY
hold time
X or Y ports setup time
X or Y ports hold time
WTA, WTB,
SOBFP or EOPSS
setup time
WTA, WTB,
SOBFP or EOPSS
hold time
CONX or CONY setup time
CONX or CONY hold time
AR15:13 or AI15:13 setup time
AR15:13 or AI15:13 hold time
OSEL to valid P ports
OER or OEI
high to PR or PI high to high Z
OER or OEI
low to PR or PI low to high Z
OER or OEI
low to PR or PI high Z to high
OER or OEI
high to PR or PI high Z to low
CLK frequency
CLK period
CLK high time
CLK low time
V
DD
current (CMOS input levels)
V
DD
current (TTL input levels)
Characteristic
Switching Characteristics
Symbol
t
CP
t
CW
t
CG
t
CSFTA
t
CSFTR
t
CES
t
CEH
t
DS
t
DH
t
WS
t
WH
t
CONS
t
CONH
t
AS
t
AH
t
OP
t
OPHZ
t
OPLZ
t
OPZH
t
OPZL
f
CLK
t
CLK
t
CLKH
t
CLKL
I
DDC
I
DDT
Max.
Min.
Max.
Min.
45
30
30
60
50
-
0
-
2
-
0
-
0
-
0
35
35
45
22
24
10
-
-
-
60
100
5
5
5
5
5
11
-
11
-
14
-
14
-
14
-
-
-
-
-
-
100
30
20
-
-
PDSP16116A
5
5
5
5
5
8
-
8
-
8
-
8
-
8
-
-
-
-
-
-
50
12
12
-
-
23
20
20
30
28
-
0
-
0
-
0
-
0
-
0
20
25
25
18
18
20
-
-
-
80
130
PDSP16116
Conditions
NOTES
1. V
=
1
5·5V, outputs unloaded, clock frequency = Max.
2. The PDSP16116B is specified as the PDSP16116A except that the maximum clock frequency is guaranteed at 25MHz, with a minimum
clock period of 40ns.
Fig.
9
9
9
9
9
9
9
9
9
9
10, 11
10, 11
10, 11
10, 11
9
9
9
Max.
Min.
PDSP16116D
5
5
5
5
5
8
-
8
-
8
-
8
-
8
-
-
-
-
-
-
31·7
12
12
-
-
23
20
20
30
28
-
0
-
2
-
0
-
0
-
2
20
25
25
18
18
31·5
-
-
-
80
130
Units
30pF
30pF
30pF
30pF
30pF
30pF
See Note 1
See Note 1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
mA
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