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參數(shù)資料
| 型號： | PDSP16116MC |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | 16 By 16 Bit Complex Multiplier(16×16位 復雜乘法器) |
| 中文描述： | 16到16位復雜乘數(shù)（16 × 16位復雜乘法器） |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 131K |
| 代理商： | PDSP16116MC |
PDSP16116/A/MC
13
The butterfly operation
The butterfly operation is the arithmetic operation which is
repeated many times to produce an FFT. The PDSP16116A
based butterfly processor performs this operation in a low
power high accuracy chip set.
A new butterfly operation is commenced each cycle,
requiring a new set of data for , B, W, WTA and WTB. Five
cycles later, the corresponding results A' and B' are produced
along with their associated WTOUT. In between, the signals
SFTA and SFTR are produced and acted upon by the shifters
in the PDSP1601/A and PDSP16318/A. The timing of the data
and control signals is shown in Fig.6.
The results (A' and B') of each butterfly calculation in a
pass must be stored away to be used later as the input data
(A and B) in the next pass. Each result must be stored together
with its associated word tag, WTOUT. Although WTOUT is
common to both A' and B', it must be stored separately with
each word as the words are used on different cycles during the
next pass. At the inputs, the word tag associated with the A
word is known as WTA and the word tag associated with the
B word is known as WTB. Hence, the WTOUTs from one pass
will become the WTAs and WTBs for the following pass. It
should be noted that the first pass is unique in that word tags
need not be input into the butterfly as all data initially has the
same weighting. Hence, during the first pass alone, the inputs
WTA and WTB are ignored.
Fig.6 Butterfly Operation
W
B
B'
A
A'
A' = A + B. W
B' = A - B. W
Fig.7 Butterfly Data and Control Signals
n-2
n-1
n
n+1
n+2
n+3
n
n+1
n+2
n+3
n+4
n+5
n
n+1
n+2
n+3
n+4
n+5
n
n+1
n+2
n+3
n+4
n+5
n-3
n-2
n-1
n
n+1
n+2
n-2
n-1
n-1
n
n+1
n+2
n-3
n-2
n-1
n
n+1
n+2
n-5
n-4
n-3
n-2
n-1
n
n-5
n-4
n-3
n-2
n-1
n
CLK
Present Br, Bi,
Wr, Wi to inputs
Present WTA,
WTB to inputs
Present Ar,
Ai to inputs
Output SFTA
Output SFTR
Output Pr, Pi
Output DAr, DAi
Output WTOUT
Output A'r, A'i, B'r, B'i
相關PDF資料 |
PDF描述 |
|---|---|
| PDSP16116 | 16 By 16 Bit Complex Multiplier(16×16位 復雜乘法器) |
| PDSP16256C0 | Programmable FIR Filter |
| PDSP16256GC1R | Programmable FIR Filter |
| PDSP16256 | Programmable FIR Filter(可編程快速脈沖響應（FIR）濾波器) |
| PDSP16256A | Programmable FIR Filter(可編程快速脈沖響應（FIR）濾波器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PDSP16116MCAC1R | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:16 by 16 Bit Complex Multiplier |
| PDSP16116MCGC1R | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:16 by 16 Bit Complex Multiplier |
| PDSP16116MCGGDR | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:16 X 16 Bit Complex Multiplier |
| PDSP16256 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Programmable FIR Filter |
| PDSP16256/A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:I/Q Splitter/NCO |
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