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CHAPTER 23 LOW-VOLTAGE DETECTOR
User’s Manual U16228EJ2V0UD
416
23.4 Operation of Low-Voltage Detector
The low-voltage detector can be used in the following two modes.
Used as reset
Compares the supply voltage (V
DD
) and detection voltage (V
LVI
), and generates an internal reset signal when
V
DD
< V
LVI
.
Used as interrupt
Compares the supply voltage (V
DD
) and detection voltage (V
LVI
), and generates an interrupt signal (INTLVI)
when V
DD
< V
LVI
.
The operation is set as follows.
(1) When used as reset
When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection
register (LVIS).
<3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator
operation).
<4> Use software to instigate a wait of at least 2 ms.
<5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<6> Use software to instigate a wait of at least 0.2 ms.
<7> Wait until it is checked that (supply voltage (V
DD
) > detection voltage (V
LVI
)) by bit 0 (LVIF) of LVIM.
<8> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (V
DD
) < detection
voltage (V
LVI
)).
Figure 23-4 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers
in this timing chart correspond to <1> to <8> above.
Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately
after the processing in <5>.
2. If “POC used” is selected by a mask option, procedures <3> and <4> are not required.
3. If supply voltage (V
DD
) > detection voltage (V
LVI
) when LVIM is set to 1, an internal reset
signal is not generated.
When stopping operation
Either of the following procedures must be executed.
Write 00H to LVIM.
Clear LVIMD to 0, LVION to 0, and LVIE to 0 in that order.
When using 8-bit memory manipulation instruction:
When using 1-bit memory manipulation instruction: