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CHAPTER 17 INTERRUPT FUNCTIONS
User’s Manual U16228EJ2V0UD
366
(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon RESET input.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt
routine is entered.
IF0L, IF0H, IF1L, and IF1H are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H, and
IF1L and IF1H are combined to form 16-bit registers IF0 and IF1, they are read with a 16-bit memory
manipulation instruction.
RESET input clears these registers to 00H.
Figure 17-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H)
Address: FFE0H After reset: 00H R/W
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IF0L
SREIF6
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
LVIIF
Address: FFE1H After reset: 00H R/W
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IF0H
TMIF010
TMIF000
TMIF50
TMIFH0
TMIFH1
DUALIF0
STIF6
SRIF6
Address: FFE2H After reset: 00H R/W
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IF1L
PIF7
PIF6
WTIF
KRIF
TMIF51
WTIIF
SRIF0
ADIF
Address: FFE3H After reset: 00H R/W
Symbol
7
6
5
4
<3>
<2>
<1>
<0>
IF1H
0
Note 1
0
Note 1
0
Note 1
0
Note 1
TMIF011
Note 2
TMIF001
Note 2
CSIIF11
Note 2
DMUIF
XXIFX
Interrupt request flag
0
No interrupt request signal is generated
1
Interrupt request is generated, interrupt request status
Notes 1.
Be sure to set bits 4 to 7 of IF1H to 0.
2.
μ
PD780133, 780134, 78F0134, 780136, 780138, and 78F0138 only. Be sure to set the
μ
PD780131
and 780132 to 0.
Cautions 1. When operating a timer, serial interface, or A/D converter after standby release, operate it
once after clearing the interrupt request flag. An interrupt request flag may be set by noise.
2. If an interrupt request corresponding to a flag of the interrupt request flag register is
generated while the interrupt request flag register is being manipulated (including by 1-bit
memory manipulation), the flag corresponding to the interrupt request may not be set to 1.