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參數(shù)資料
| 型號(hào)： | PCM3794RHBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁(yè)數(shù)： | 39/67頁(yè) |
| 文件大?。?/td> | 1417K |
| 代理商： | PCM3794RHBT |
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www.ti.com
SLES193C – AUGUST 2006 – REVISED FEBRUARY 2007
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 84
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
MSTR
RSV
BIT0
Register 85
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
SRST
RSV
NPR5
NPR4
NPR3
NPR2
NPR1
NPR0
Register 86
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
MBST
MSR2
MSR1
MSR0
ATOD
RSV
ZCRS
IDX[6:0]: 101 0100b (54h): Register 84
IDX[6:0]: 101 0101b (55h): Register 85
IDX[6:0]: 101 0110b (56h): Register 86
MSTR: Master or Slave Selection for Audio Interface
Default value: 0
This bit is used to select either master or slave mode for the audio interface. In master mode, the PCM3793/94
generates LRCK and BCK from the system clock. In slave mode, it receives LRCK and BCK from another
device.
MSTR = 0
Slave interface (default)
MSTR = 1
Master interface
BIT0: Bit Length Selection for Audio Interface
Default value: 1
This bit is used to select the data bit length for DAC input.
BIT0 = 0
Reserved
BIT0 = 1
16 bits (default)
SRST: System Reset
Default value: 0
This bit is used to enable system reset. All circuits are reset by setting SRST = 1. After completing the reset
sequence, SRST is set to 0 automatically.
SRST = 0
Reset disabled (default)
SRST = 1
Reset enabled
NPR[5:0]: System Clock Rate Selection
Default value: 000000
MSR[2:0]: System Clock Dividing Rate Selection in Master Mode (Register 70)
Default value: 000
These bits are used to select the system clock rate and the dividing rate of the input system clock. See Table 12
for the details.
44
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