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參數(shù)資料
型號(hào)： PCM3168ATPAPRQ1G4
廠商： Texas Instruments
文件頁(yè)數(shù)： 25/68頁(yè)
文件大?。?/td> 0K
描述： IC 24-BIT AUDIO CODEC 64-HTQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 6 / 8
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 107 / 112（差分），104 / 112（單端）
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 107 / 112（差分），104 / 112（單端）
電壓 - 電源，模擬： 4.5 V ~ 5.5 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-HTQFP（10x10）
包裝： 帶卷 (TR)
FOUR-WIRE (SPI) SERIAL CONTROL
CONTROL DATA WORD FORMAT
ADR6
R/W
RegisterAddress
RegisterData
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008
The de-emphasis filter is enabled by the MDI/SDA/DEMP pin. The de-emphasis frequency is fixed at 44.1 kHz in
hardware control mode, as shown in Table 13. The software mode provides full selections of 32 kHz, 44.1 kHz,
and 48 kHz.
Table 13. Hardware Control Mode
DEMP (DE-EMPHASIS FILTER ENABLE)
DESCRIPTION
Low
44.1 kHz, de-emphasis disabled
High
44.1 kHz, de-emphasis enabled
The audio interface and the sampling mode are selected by the MS/ADR0/MD0 and MDO/ADR1/MD1 pins. The
selectable multiple of the master mode audio interface is limited between 256 fS, 384 fS, and 512 fS; the
selectable sampling mode is limited as shown in Table 14. The software mode provides full selections.
Table 14. Selectable Sampling Mode
DESCRIPTION
INTERFACE MODE
SAMPLING MODE
MD1
MD0
ADC
DAC
ADC
DAC
Low
Slave(1)
Auto(2)
Low
High
Master, 512 fS
Slave(1)
Single rate
Auto(2)
High
Low
Master, 384 fS
Slave(1)
Dual rate
Auto(2)
High
Master, 256 fS
Slave(1)
Dual rate
Auto(2)
(1)
The multiples between system clock and sampling frequency are automatically detected; 256 fS, 384 fS, 512 fS, and 768 fS are
acceptable for ADC operation, and 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, and 768 fS are acceptable for DAC operation.
(2)
The sampling mode is automatically set as single rate for 512 fS and 768 fS, dual rate for 256 fS and 384 fS, and quad rate for 128 fS and
198 fS, according to the detected multiples between the system clock and sampling clock.
The PCM3168A and PCM3168A-Q1 include an SPI-compatible serial port that operates asynchronously with the
audio serial interface. The control interface consists of MDI/SDA/DEMP, MDO/ADR1/MD1, MC/SCL/FMT, and
MS/ADR0/MD0. MDI is the serial data input to program the mode control registers. MDO is the serial data output
to read back register settings and some flags. MDO is inactive (Hi-Z, high impedance) during MS = high. MC is
the serial bit clock that shifts the data into the control port. MS is the select input to enable the mode control port.
All single write/read operations via the serial control port use 16-bit data words. Figure 47 shows the control data
word format. The first bit is for read/write controls; '0' indicates a write operation and '1' indicates a read
operation. Following the first bit are seven other bits, labeled ADR[6:0] that set the register address for the
write/read operation. The eight least significant bits (LSBs), D[7:0] on MDI or MDO, contain the data to be written
to the register specified by ADR[6:0], or the data read from the register specified by ADR[6:0].
Figure 47. Control Data Word Format for MDI
Copyright 2008, Texas Instruments Incorporated
31
Product Folder Link(s): PCM3168A PCM3168A-Q1
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