參數(shù)資料
型號： PCM3052ARTFG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 編解碼器
英文描述： PCM CODEC, PQCC32
封裝： GREEN, PLASTIC, VQFN-32
文件頁數(shù)： 27/47頁
文件大?。?/td> 776K
代理商： PCM3052ARTFG4
www.ti.com
TIMING DIAGRAM
SDA
SCL
t(BUF)
t(D-SU)
t(D-HD)
Start
t(LOW)
t(S-HD)
t(SCL-F)
t(SCL-R)
t(HI)
Repeated Start
t(RS-SU)
t(RS-HD)
t(SDA-F)
t(SDA-R)
t(P-SU)
Stop
T0050-01
MODE CONTROL REGISTERS
User-Programmable Mode Controls
PCM3052A
SLES160 – NOVEMBER 2005
PARAMETER
CONDITIONS
MIN
MAX
UNIT
f(SCL)
SCL clock frequency
Standard mode
100
kHz
t(BUF)
Bus free time between STOP and START condition
Standard mode
4.7
s
t(LOW)
Low period of the SCL clock
Standard mode
4.7
s
t(HI)
High period of the SCL clock
Standard mode
4
s
tRS-SU
Setup time for START/repeated START condition
Standard mode
4.7
s
t(S-HD)
Hold time for START/repeated START condition
Standard mode
4
s
t(RS-HD)
t(D-SU)
Data setup time
Standard mode
250
ns
t(D-HD)
Data hold time
Standard mode
0
900
ns
t(SCL-R)
Rise time of SCL signal
Standard mode
20 + 0.1 CB
1000
ns
t(SCL-R1)
Rise time of SCL signal after a repeated START condition and after
Standard mode
20 + 0.1 CB
1000
ns
an acknowledge bit
t(SCL-F)
Fall time of SCL signal
Standard mode
20 + 0.1 CB
1000
ns
t(SDA-R)
Rise time of SDA signal
Standard mode
20 + 0.1 CB
1000
ns
t(SDA-F)
Fall time of SDA signal
Standard mode
20 + 0.1 CB
1000
ns
t(P-SU)
Setup time for STOP condition
Standard mode
4
s
CB
Capacitive load for SDA and SCL line
400
pF
VNH
Noise margin at high level for each connected device (including
Standard mode
0.2 VDD
V
hysteresis)
Figure 55. Control Interface Timing
The PCM3052A has several user programmable functions which are accessed via control registers. The
registers are programmed using the I2C serial control port, which was previously discussed in this data sheet.
Table 4 lists the available mode control functions, along with their reset default conditions and associated register
addresses. The register map is shown in Table 5.
33
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