參數(shù)資料
型號: PCM3052ARTFG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 編解碼器
英文描述: PCM CODEC, PQCC32
封裝: GREEN, PLASTIC, VQFN-32
文件頁數(shù): 24/47頁
文件大?。?/td> 776K
代理商: PCM3052ARTFG4
www.ti.com
T0099-01
SW
DIN
(I2S Format)
A
C
P
Pa
U
V
R-ch
L-ch
Frame
R-ch
Frame
SW
A
P
L-ch
Frame
R-ch
Enable
LOW
Disable
L-ch
Frame
S/PDIF Output
Control Bit
DOUTS
P: Preamble
A: Aux
U: User Bits
C: Channel Status
SW: Audio Sample Word
V: Validity Bit
Pa: Parity Bit
A
C
P
Pa
U
V
32/fS
Frame
PCM3052A
SLES160 – NOVEMBER 2005
Each bit after the audio sample word is assigned in the PCM3052A as follows.
Validity bit:
Writable through serial control port
User data:
Fixed to 0
Channel status [0]:
Fixed to 0 (consumer use)
Channel status [1]:
Writable through serial control port (audio sample word type)
Channel status [2]:
Writable through serial control port (copyright flag)
Channel status [3:5]:
Writable through serial control port (additional format information)
Channel status [6:7]:
Fixed to 00 (mode 0)
Channel status [8:15]:
Writable through serial control port (category code)
Channel status [16:19]:
Fixed to 0000 (source number)
Channel status [20:23]:
Fixed to 0000 (channel number)
Channel status [24:27]:
Writable through serial control port (sampling frequency)
Channel status [28:29]:
Writable through serial control port (clock accuracy)
Channel status [30:31]:
Fixed to 00
Channel status [32:35]:
Writable through serial control port (word length)
Channel status [36:191]:
Fixed to all 0s
Parity bit:
Even parity for preceding data from preamble to channel status bit
S/PDIF output timing is shown in Figure 51. The S/PDIF block starts with a preamble after 32/fS from the frame
where S/PDIF output control bit becomes HIGH. The behavior of DOUTS for power-on reset, external reset, and
loss of synchronization is shown in Figure 44, Figure 45, and Figure 48, respectively.
Figure 51. S/PDIF Output Timing
30
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