參數(shù)資料
型號: PCA9698DGG/S911,51
廠商: NXP Semiconductors
文件頁數(shù): 29/48頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 40B 56TSSOP
標準包裝: 2,000
接口: I²C
輸入/輸出數(shù): 40
中斷輸出:
頻率 - 時鐘: 1MHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應商設備封裝: 56-TSSOP
包裝: 帶卷 (TR)
包括: POR
其它名稱: 935285491518
PCA9698DGG/S911-T
PCA9698DGG/S911-T-ND
35
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
To avoid unintentional changes of clock frequency, a special write procedure must befollowed to
change the CLKPS bits:
1.
Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bitsin
CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
8.12
Register Description
8.12.1
OSCCAL – Oscillator Calibration Register
Bits 7..0 – CAL7..0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. A pre-programmed calibration value is
automatically written to this register during chip reset, giving the Factory calibrated frequency as
specified in Table 28-1 on page 307. The application software can write this register to change
the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table
28-1 on page 307. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more
than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the
range.
8.12.2
CLKPR – Clock Prescale Register
Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
Bit
7
65
43
21
0
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
OSCCAL
Read/Write
R/W
Initial Value
Device Specific Calibration Value
Bit
7
6
5
4
3210
CLKPCE
CLKPS3
CLKPS2
CLKPS1
CLKPS0
CLKPR
Read/Write
R/W
R
R/W
Initial Value
0
See Bit Description
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