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參數(shù)資料
| 型號(hào)： | PCA9698DGG,512 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 28/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 40B 56TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | I²C Bus Fundamentals |
| 特色產(chǎn)品： | NXP - I2C Interface |
| 標(biāo)準(zhǔn)包裝： | 35 |
| 接口： | I²C |
| 輸入/輸出數(shù)： | 40 |
| 中斷輸出： | 是 |
| 頻率 - 時(shí)鐘： | 1MHz |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 管件 |
| 包括： | POR |
| 產(chǎn)品目錄頁面： | 826 (CN2011-ZH PDF) |
| 其它名稱： | 568-3241-5 935278614512 PCA9698DGG |
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34
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is
required, ensure that the MCU is kept in Reset during the changes.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page
34 for details.
8.9
Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal RC
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
8.10
Timer/Counter Oscillator
ATmega328P uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter
Oscillator. See “Low Frequency Crystal Oscillator” on page 31 for details on the oscillator and
crystal requirements.
ATmega328P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and
XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the
oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only be
used when the Calibrated Internal RC Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is
written to logic one. See “Asynchronous Operation of Timer/Counter2” on page 147 for further
description on selecting external clock as input instead of a 32.768 kHz watch crystal.
8.11
System Clock Prescaler
The ATmega328P has a system clock prescaler, and the system clock can be divided by setting
the “CLKPR – Clock Prescale Register” on page 357. This feature can be used to decrease the
system clock frequency and the power consumption when the requirement for processing power
is low. This can be used with all clock source options, and it will affect the clock frequency of the
CPU and all synchronous peripherals. clk
I/O, clkADC, clkCPU, and clkFLASH are divided by a factor
as shown in Table 28-4 on page 308.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting. The ripple counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it
is not possible to determine the state of the prescaler - even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. From the
time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the pre-
vious clock period, and T2 is the period corresponding to the new prescaler setting.
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參數(shù)描述 |
|---|---|
| PCA9698DGGS911,51 | 功能描述:I2C 接口集成電路 40-bit Fm I2C Bus I/O port w/Reset RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| PCA9698DGGT | 制造商:NXP Semiconductors 功能描述:I2C GPIO Expander 5.5V 56-Pin TSSOP T/R |
| PCA9698DGG-T | 制造商:NXP Semiconductors 功能描述:I2C GPIO Expander 5.5V 56-Pin TSSOP T/R |
| PCA96PWS911,118 | 功能描述:接口-I/O擴(kuò)展器 8-BIT I2C FM QB RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel |
| PCA9701D | 功能描述:寄存器 16BIT SPI 18V GPI INT -40 +125 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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