參數(shù)資料
型號(hào)： PCA9698DGG,512
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 19/48頁(yè)
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 40B 56TSSOP
產(chǎn)品培訓(xùn)模塊： I²C Bus Fundamentals
特色產(chǎn)品： NXP - I2C Interface
標(biāo)準(zhǔn)包裝： 35
接口： I²C
輸入/輸出數(shù)： 40
中斷輸出： 是
頻率 - 時(shí)鐘： 1MHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 56-TFSOP（0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 56-TSSOP
包裝： 管件
包括： POR
產(chǎn)品目錄頁(yè)面： 826 (CN2011-ZH PDF)
其它名稱(chēng)： 568-3241-5
935278614512
PCA9698DGG
26
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
8.1.4
Asynchronous Timer Clock – clk
ASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows
using this Timer/Counter as a real-time counter even when the device is in sleep mode.
8.1.5
ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
8.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Note:
1. For all fuses “1” means unprogrammed while “0” means programmed.
8.2.1
Default Clock Source
The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 pro-
grammed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out
period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that
all users can make their desired clock source setting using any available programming interface.
8.2.2
Clock Startup Sequence
Any clock source needs a sufficient V
CC to start oscillating and a minimum number of oscillating
cycles before it can be considered stable.
To ensure sufficient V
CC, the device issues an internal reset with a time-out delay (tTOUT) after
the device reset is released by all other reset sources. “System Control and Reset” on page 44
describes the start conditions for the internal reset. The delay (t
TOUT) is timed from the Watchdog
Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
Table 8-1.
Device Clocking Options Select(1)
Device Clocking Option
CKSEL3..0
Low Power Crystal Oscillator
1111 - 1000
Full Swing Crystal Oscillator
0111 - 0110
Low Frequency Crystal Oscillator
0101 - 0100
Internal 128 kHz RC Oscillator
0011
Calibrated Internal RC Oscillator
0010
External Clock
0000
Reserved
0001
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