參數(shù)資料
型號(hào)： PAC7131
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Microcontroller Family Hardware Specifications
中文描述： 微控制器系列硬件規(guī)格
文件頁(yè)數(shù)： 28/56頁(yè)
文件大小： 471K
代理商： PAC7131
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Electrical Characteristics
Freescale Semiconductor
28
3.10.3 ATD Timing Specifications
Figure 10. ATD External Trigger Timing Diagram
Table 31. ATD External Trigger Timing Specifications
Num C
Parameter
Symbol
Min
Max
Unit
T1
T2
D ETRIG Period (Level-Sensitive Trigger Mode)
D ETRIG Minimum Pulse Width
Edge-Sensitive Trigger Mode
Level-Sensitive Trigger Mode
D ETRIG Level Recovery
2
D Conversion Start Delay
T
PERIOD
t
PW
1 + N
CONV
n
1
NOTES:
1. N
CONV
n
denotes 8- or 10-bit conversion time (refer to specifications
N4
,
N5
,
P4
and
P5
). In order to achieve the
minimum period between conversions when using level-sensitive triggering, ETRIG must remain asserted this long.
2. Time prior to the end of a conversion that ETRIG must be negated in order to prevent the start of another conversion.
—
f
ATDCLK
Cycles
f
ATDCLK
Cycles
1
2
1
—
—
—
—
2
T3
T4
t
LR
t
DLY
f
ATDCLK
Cycles
f
ATDCLK
Cycles
Level Sensitive
Low Active
Sequence
Complete Flag
Conversion Activity
Low Active
Sequence
Complete Flag
Conversion Activity
Level Sensitive
Falling Edge Active
Conversion Activity
Edge Sensitive
ETRIG
AN
n
_
x
ETRIG
ASCIF
AN
n
_
x
ETRIG
ASCIF
AN
n
_
x
T2
T1
T4
T4
T2
T4
T4
T4
T3
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