參數(shù)資料
型號: PAC7131
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Microcontroller Family Hardware Specifications
中文描述: 微控制器系列硬件規(guī)格
文件頁數(shù): 21/56頁
文件大?。?/td> 471K
代理商: PAC7131
Electrical Characteristics
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
21
3.9.1
Read and Write Bus Cycles
Table 25
lists processor bus output timings. Read/write bus timings listed in
Table 25
are shown in
Figure 7
and
Figure 8
.
Table 25. External Bus Output Timing Specifications
1
NOTES:
1. Assumes CLKOUT, CS
n
, BS
n
, OE, AS, ADDR[21:0] and DATA[15:0] are configured for full drive strength (via the PIM).
2. The CS
n
, BS
n
, OE and AS signals are synchronous to the falling edge of CLKOUT. Therefore, changes on these
signals are triggered by the falling edge of CLKOUT, even though they are specified in relation to the rising edge.
Num
C
Rating
Symbol
Min
Max
Unit
Control Outputs
M6a
P CLKOUT high
2
to chip selects (CS[2:0]) valid
t
CHCV
0.5t
CYC
+ 10
ns
M6b
P CLKOUT high
2
to byte selects (BS[1:0]) valid
t
CHBV
0.5t
CYC
+ 10
ns
M6c
P CLKOUT high
2
to output select (OE) valid
t
CHOV
0.5t
CYC
+ 10
ns
M6d
P CLKOUT high
2
to address strobe (AS) valid
t
CHASV
0.5t
CYC
+ 10
ns
M7a
P CLKOUT high
2
to control output (BS[1:0], OE) invalid
t
CHCOI
0.5t
CYC
+ 2
ns
M7b
P CLKOUT high
2
to chip selects (CS[2:0]) invalid
t
CHCI
0.5t
CYC
+ 2
ns
M7c
P CLKOUT high
2
to address strobe (AS) invalid
t
CHASI
0.5t
CYC
+ 2
ns
Address and Attribute Outputs
M8
P CLKOUT high to address (ADDR[21:0]) and control
(R/W) valid
t
CHAV
10
ns
M9
P CLKOUT high to address (ADDR[21:0]) and control
(R/W) invalid
t
CHAI
2
ns
Data Outputs
M10
P CLKOUT high to data output (DATA[15:0]) valid
t
CHDOV
13
ns
M11
P CLKOUT high to data output (DATA[15:0]) invalid
t
CHDOI
2
ns
M12
D
CLKOUT high to data output (DATA[15:0]) high impedance
t
CHDOZ
9
ns
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