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參數(shù)資料
| 型號： | PAC7126 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Microcontroller Family Hardware Specifications |
| 中文描述： | 微控制器系列硬件規(guī)格 |
| 文件頁數(shù)： | 20/56頁 |
| 文件大?。?/td> | 471K |
| 代理商： | PAC7126 |
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MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Electrical Characteristics
Freescale Semiconductor
20
3.9
External Bus Timing
Table 24
lists processor bus input timings, which are shown in
Figure 6
,
Figure 7
and
Figure 8
.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay
with respect to the rising edge of a reference clock. The reference clock is the
CLKOUT output. All other timing relationships can be derived from these values.
Figure 6. General Input Timing Requirements
Table 24. External Bus Input Timing Specifications
1
NOTES:
1. Assumes CLKOUT is configured for full drive strength (via the PIM CONFIG2_D[RDS] bit).
2. CLKOUT is equal to the system clock,
f
SYS
. If CLKSEL[PLLSEL] is set then
f
SYS
is equal to
f
VCO
(table
Table 20
,
K3
); if it is clear then
f
SYS
is equal to
f
OSC
(table
Table 19
,
J1a
or
J1b
). Throughout this document, t
CYC
is used to
specify a unit of time equal to 1
÷
CLKOUT (which is equal to t
fsys
).
3. The TA pin is the only control input on MAC7100 family devices.
Num
C
Rating
Symbol
Min
Max
Unit
M1
P CLKOUT period
2
t
CYC
20
—
ns
Control Inputs
M2a
P Control input valid to CLKOUT high
3
t
CVCH
13
—
ns
M3a
P CLKOUT high to control inputs invalid
3
t
CHCII
0
—
ns
Data Inputs
M4
P Data input (DATA[15:0]) valid to CLKOUT high
t
DIVCH
9
—
ns
M5
P CLKOUT high to data input (DATA[15:0]) invalid
t
CHDII
0
—
ns
CLKOUT (50 MHz)
1.5 V
1.5 V
Valid
Invalid
Invalid
t
SETUP
t
HOLD
Input Setup & Hold
Input Rise Time
V
H
= V
IH
V
L
= V
IL
t
RISE
= 1.5 ns
Input Fall Time
V
H
= V
IH
V
L
= V
IL
t
FALL
= 1.5 ns
CLKOUT
Inputs
1.5 V
M4
M5
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