參數(shù)資料
型號(hào)： PA28F800B5T70
廠商： INTEL CORP
元件分類： PROM
英文描述： SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT
中文描述： 1M X 8 FLASH 5V PROM, 80 ns, PDSO44
封裝： 0.525 X 1.110 INCH, PLASTIC, SOP-44
文件頁數(shù)： 33/38頁
文件大?。?/td> 501K
代理商： PA28F800B5T70
E
5.7
SMART 5 BOOT BLOCK MEMORY FAMILY
33
ADVANCE INFORMATION
AC Characteristics
—Write Operations—Commercial and Extended
Temperature
Comm
Extended
#
Sym
Parameter
Note
Min
Max
Min
Max
Unit
W1
t
PHWL
(t
PHEL
)
RP# High Recovery to WE# (CE#) Going
Low
450
450
ns
W2
t
ELWL
(t
WLEL
)
CE# (WE#) Setup to WE# (CE#) Going
Low
0
0
ns
W3
t
WP
Write Pulse Width
9
50
60
ns
W4
t
DVWH
(t
DVEH
)
Data Setup to WE# (CE#) Going High
4
50
60
ns
W5
t
AVWH
(t
AVEH
)
Address Setup to WE# (CE#) Going High
3
50
60
ns
W6
t
WHEH
(t
EHWH
)
CE# (WE#) Hold from WE# (CE#) High
0
0
ns
W7
t
WHDX
(t
EHDX
)
Data Hold from WE# (CE#) High
4
0
0
ns
W8
t
WHAX
(t
EHAX
)
Address Hold from WE# (CE#) High
3
0
0
ns
W9
t
WPH
Write Pulse Width High
V
CC
= 5 V
±
5%
10
10
ns
V
CC
= 5 V
±
10%
20
20
ns
W10 t
PHHWH
(t
PHHEH
)
RP# V
HH
Setup to WE# (CE#) Going High
6,8
100
100
ns
W11 t
VPWH
(t
VPEH
)
V
PP
Setup to WE# (CE#) Going High
5,8
100
100
ns
W12 t
QVPH
RP# V
HH
Hold from Valid SRD
6,8
0
0
ns
W13 t
QVVL
V
PP
Hold from Valid SRD
5,8
0
0
ns
W14 t
PHBR
Boot Block Lock Delay
7,8
100
100
ns
NOTES:
1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC
Characteristics
—Read-Only Operations.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify operations.
3. Refer to command definition table for valid A
IN
. (Table 6)
4. Refer to command definition table for valid D
IN
. (Table 6)
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For boot block program/erase, RP# should be held at V
HH
or WP# should be held at V
IH
until operation completes
successfully.
7. Time t
PHBR
is required for successful locking of the boot block.
8. Sampled, but not 100% tested.
9. Write pulse width (t
) is defined from CE# or WE# going low (whichever goes low last)
to CE# or WE# going high
(whichever goes high first). Hence, t
WP
= t
WLWH
= t
ELEH
= t
WLEH
= t
ELWH
.
10. Write pulse width high (t
) is defined from CE# or WE# going high (whichever goes high first)
to CE# or WE# going low
(whichever goes low first). Hence, t
WPH
= t
WHWL
= t
EHEL
= t
WHEL
= t
EHWL
.
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