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參數(shù)資料
| 型號(hào)： | PA28F400B5B60 |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | PROM |
| 英文描述： | COUPLER, HYBRID, 3DB, 90DEG |
| 中文描述： | 512K X 8 FLASH 5V PROM, 70 ns, PDSO44 |
| 封裝： | 0.525 X 1.110 INCH, PLASTIC, SOP-44 |
| 文件頁(yè)數(shù)： | 25/38頁(yè) |
| 文件大?。?/td> | 501K |
| 代理商： | PA28F400B5B60 |
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E
4.1.3
SMART 5 BOOT BLOCK MEMORY FAMILY
25
ADVANCE INFORMATION
STANDBY POWER
When CE# is at a logic-high level (V
IH
), and the
device is not programming or erasing, the memory
enters in standby mode, which disables much of the
device’s circuitry and substantially reduces power
consumption. Outputs (DQ
0
–DQ
15
or DQ
0
–DQ
7
) are
placed in a high-impedance state independent of
the status of the OE# signal. When CE# is at logic-
high level during program or erase operations, the
device will continue to perform the operation and
consume corresponding active power until the
operation is completed.
4.1.4
DEEP POWER-DOWN MODE
The Smart 5 boot block family supports a low
typical I
CCD
in deep power-down mode, which turns
off all circuits to save power. This mode is activated
by the RP# pin when it is at a logic-low (GND
±
0.2 V).
Note: BYTE# pin must be at CMOS levels to
meet the I
CCD
specification.
During read modes, the RP# pin going low de-
selects the memory and places the output drivers in
a high impedance state. Recovery from the deep
power-down state, requires a minimum access time
of t
PHQV
. RP# transitions to V
, or turning power off
to the device will clear the status register.
During an program or erase operation, RP# going
low for time t
PLPH
will abort the operation, but the
location’s memory contents will no longer valid and
additional timing must be met. See Section 3.1.5
and Figure 15 and Table 9 for additional
information.
4.2
Power-Up/Down Operation
The device protects against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, so either
V
PP
or V
CC
can power-up first. The CUI defaults to
the read mode after power-up, but the system must
drop CE# low or present an address to receive valid
data at the outputs.
A system designer must guard against spurious
writes when V
CC
voltages are above V
LKO
and V
PP
is active. Since both WE# and CE# must be low for
a command write, driving either signal to V
IH
will
inhibit writes to the device. Additionally, alteration of
memory can only occur after successful completion
of a two-step command sequences. The device is
also disabled until RP# is brought to V
IH
, regardless
of the state of its control inputs. By holding the
device in reset (RP# connected to system
PowerGood) during power-up/down, invalid bus
conditions during power-up can be masked,
providing yet another level of memory protection.
4.2.1
RP# CONNECTED TO SYSTEM
RESET
Using RP# properly during system reset is
important with automated program/erase devices
because the system expects to read from the flash
memory when it comes out of reset. If a CPU reset
occurs without a flash memory reset, proper CPU
initialization would not occur because the flash
memory may in a mode other than Read Array.
Intel’s
Flash
memories
initialization following a system reset by connecting
the RP# pin to the same RESET# signal that resets
the system CPU.
allow
proper
CPU
4.3
Board Design
4.3.1
POWER SUPPLY DECOUPLING
Flash memory’s switching characteristics require
careful decoupling methods. System designers
should consider three supply current issues:
standby current levels (I
CCS
), active current levels
(I
CCR
), and transient peaks produced by falling and
rising edges of CE#.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 μF ceramic
capacitor connected between V
CC
and GND, and
between V
PP
and GND. These high-frequency,
inherently low-inductance capacitors should be
placed as close as possible to the package leads.
4.3.2
V
TRACE ON PRINTED CIRCUIT
BOARDS
In-system updates to the flash memory requires
special consideration of the V
PP
power supply trace
by the printed circuit board designer. Since the V
PP
pin supplies the current for programming and
erasing, it should have similar trace widths and
layout considerations as given to the V
CC
power
supply trace. Adequate V
PP
supply traces, and
decoupling capacitors placed adjacent to the
component, will decrease spikes and overshoots.
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| PA28F800B5T90 | SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
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| PA28F200B5B80 | SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PA28F400B5B80 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
| PA28F400B5T60 | 制造商:Intel 功能描述: |
| PA28F400B5T80 | 制造商:Intel 功能描述:Flash Mem Parallel 5V 4M-Bit 512K x 8/256K x 16 80ns 44-Pin SOP |
| PA28F400BL-B150 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:4-MBlT (256K x 16, 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F400BL-T150 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:4-MBlT (256K x 16, 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
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