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參數(shù)資料
| 型號： | PA28F400B5B60 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | COUPLER, HYBRID, 3DB, 90DEG |
| 中文描述： | 512K X 8 FLASH 5V PROM, 70 ns, PDSO44 |
| 封裝： | 0.525 X 1.110 INCH, PLASTIC, SOP-44 |
| 文件頁數(shù)： | 24/38頁 |
| 文件大?。?/td> | 501K |
| 代理商： | PA28F400B5B60 |
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SMART 5 BOOT BLOCK MEMORY FAMILY
E
24
ADVANCE INFORMATION
3.3
Boot Block Locking
The boot block family architecture features a
hardware-lockable boot block so that the kernel
code for the system can be kept secure while the
parameter and main blocks are programmed and
erased independently as necessary. Only the boot
block can be locked independently from the other
blocks.
3.3.1
V
= V
FOR COMPLETE
PROTECTION
For complete write protection of all blocks in the
device, the V
PP
voltage can be held low. When V
is below V
, any program or erase operation will
result in a error in the status register.
3.3.2
WP# = V
IL
FOR BOOT BLOCK
LOCKING
When WP# = V
IL
, the boot block is locked and any
program or erase operation to the boot block will
result in an error in the status register. All other
blocks remain unlocked in this condition and can be
programmed or erased normally. Note that this
feature is overridden and the boot block unlocked
when RP# = V
HH
.
3.3.3
RP# = V
OR WP# = V
IH
FOR BOOT
BLOCK UNLOCKING
Two methods can be used to unlock the boot block:
1.
WP# = V
IH
2.
RP# = V
HH
If both or either of these two conditions are met, the
boot block will be unlocked and can be
programmed or erased.
The Write Proctection Truth Table Table 8, clearly
defines the write protection methods.
3.3.4
NOTE FOR 8-MBIT 44-PSOP
PACKAGE
The 8-Mbit in the 44-PSOP package does not have
a WP# because no other pins were available for the
8-Mbit upgrade address. Thus, in this density-
package combination only, V
HH
(12 V) on RP# is
required to unlock the boot block and unlocking with
a logic-level signal is not possible. If this unlocking
functionality is required, and 12 V is not available
in-system, please consider using the 48-TSOP
package, which has a WP# pin and can be
unlocked with a logic-level signal. All other density-
package combinations have WP# pins.
Table 8. Write Protection Truth Table
V
PP
RP#
WP#
Write Protection
Provided
V
IL
X
X
All Blocks Locked
≥
V
PPLK
V
IL
X
All Blocks Locked
(Reset)
≥
V
PPLK
V
HH
X
All Blocks Unlocked
≥
V
PPLK
V
IH
V
IL
Boot Block Locked
≥
V
PPLK
V
IH
V
IH
All Blocks Unlocked
4.0
DESIGN CONSIDERATIONS
The following section discusses recommended
design considerations which can improve the
robustness of system designs using flash memory.
4.1
Power Consumption
Intel flash components contain features designed to
reduce power requirements. The following sections
will detail how to take advantage of these features.
4.1.1
ACTIVE POWER
Asserting CE# to a logic-low level and RP# to a
logic-high level places the device in the active
mode. Refer to the DC Characteristics table for I
CCR
current values.
4.1.2
AUTOMATIC POWER SAVINGS (APS)
Automatic Power Savings (APS) provides low-
power operation in active mode. Power Reduction
Control (PRC) circuitry allows the device to put
itself into a low current state when not being
accessed. After data is read from the memory
array, PRC logic controls the device’s power
consumption by entering the APS mode where
typical I
CC
current is less than 1 mA. The device
stays in this static state with outputs valid until a
new location is read.
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| PA28F800B5T90 | SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PA28F400B5B80 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
| PA28F400B5T60 | 制造商:Intel 功能描述: |
| PA28F400B5T80 | 制造商:Intel 功能描述:Flash Mem Parallel 5V 4M-Bit 512K x 8/256K x 16 80ns 44-Pin SOP |
| PA28F400BL-B150 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBlT (256K x 16, 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F400BL-T150 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBlT (256K x 16, 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
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