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參數(shù)資料
| 型號： | PA28F200CV-B80 |
| 廠商： | Intel Corp. |
| 英文描述： | 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 2兆位SmartVoltage啟動塊閃存系列 |
| 文件頁數(shù)： | 21/48頁 |
| 文件大小： | 562K |
| 代理商： | PA28F200CV-B80 |
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28F200BX-T/B, 28F002BX-T/B
4.4.3.1 Status Register Bit Definition
Table 5. Status Register Definitions
WSMS
ESS
ES
PS
VPPS
R
R
R
7
6
5
4
3
2
1
0
NOTES:
SR.7
e
WRITE STATE MACHINE STATUS
1
e
Ready
0
e
Busy
Write State Machine Status bit must first be checked to
determine byte/word program or block erase completion,
before the Program or Erase Status bits are checked for
success.
SR.6
e
ERASE SUSPEND STATUS
1
e
Erase Suspended
0
e
Erase in Progress/Completed
When Erase Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to ‘‘1’’. ESS bit re-
mains set to ‘‘1’’ until an Erase Resume command is is-
sued.
SR.5
e
ERASE STATUS
1
e
Error in Block Erasure
0
e
Successful Block Erase
When this bit is set to ‘‘1’’. WSM has applied the maxi-
mum number of erase pulses to the block and is still un-
able to successfully perform an erase verify.
SR.4
e
PROGRAM STATUS
1
e
Error in Byte/Word Program
0
e
Successful Byte/Word Program
When this bit is set to ‘‘1’’, WSM has attempted but failed
to Program a byte or word.
SR.3
e
V
PP
STATUS
1
e
V
PP
Low Detect; Operation Abort
0
e
V
PP
OK
The V
PP
Status bit, unlike an A/D converter, does not
provide continuous indication of V
PP
level. The WSM in-
terrogates the V
PP
level only after the byte write or block
erase command sequences have been entered and in-
forms the system if V
PP
has not been switched on. The
V
PP
Status bit is not guaranteed to report accurate feed-
back between V
PPL
and V
PPH
.
SR.2–SR.0
e
RESERVED FOR FUTURE ENHANCE-
MENTS
These bits are reserved for future use and should be
masked out when polling the Status Register.
4.4.3.2 Clearing the Status Register
Certain bits in the status register are set by the write
state machine, and can only be reset by the system
software. These bits can indicate various failure con-
ditions. By allowing the system software to control
the resetting of these bits, several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in se-
quence). The status register may then be read to
determine if an error occurred during that program-
ming or erasure series. This adds flexibility to the
way the device may be programmed or erased. To
clear the status register, the Clear Status Register
command is written to the CUI. Then, any other
command may be issued to the CUI. Note again that
before a read cycle can be initiated, a Read Array
command must be written to the CUI to specify
whether the read data is to come from the array,
status register, or Intelligent Identifier.
4.4.4 PROGRAM MODE
Program is executed by a two-write sequence. The
Program Setup command is written to the CUI fol-
lowed by a second write which specifies the address
and data to be programmed. The write state ma-
chine will execute a sequence of internally timed
events to:
1. Program the desired bits of the addressed memo-
ry word (byte), and
2. Verify that the desired bits are sufficiently pro-
grammed
Programming of the memory results in specific bits
within a byte or word being changed to a ‘‘0’’.
If the user attempts to program ‘‘1’’s, there will be no
change of the memory cell content and no error oc-
curs.
Similar to erasure, the status register indicates
whether programming is complete. While the pro-
gram sequence is executing, bit 7 of the status regis-
ter is a ‘‘0’’. The status register can be polled by
21
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