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參數(shù)資料
| 型號(hào)： | PA28F200BL-T150 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 2-MBIT (128K x 16, 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 128K X 16 FLASH 12V PROM, 150 ns, PDSO44 |
| 封裝： | 1.110 X 0.525 INCH, PLASTIC, SOP-44 |
| 文件頁數(shù)： | 44/48頁 |
| 文件大?。?/td> | 562K |
| 代理商： | PA28F200BL-T150 |
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28F200BX-T/B, 28F002BX-T/B
AC CHARACTERISTICS FOR CE
Y
-CONTROLLED WRITE OPERATIONS
(1, 9)
Versions
V
CC
g
5%
28F200BX-60
(10)
28F200BX-60
(11)
28F200BX-80
(11)
28F200BX-120
(11)
28F002BX-60
(10)
28F002BX-60
(11)
28F002BX-80
(11)
28F002BX-120
(11)
V
CC
g
10%
Unit
Symbol
Parameter
Notes
Min
Max
Min
Max
Min
Max
Min
Max
t
AVAV
t
PHEL
t
WC
Write Cycle Time
t
PS
RP
Y
High Recovery
to CE
Y
Going Low
60
70
80
120
ns
215
215
215
215
ns
t
WLEL
t
WS
WE
Y
Setup to CE
Y
Going Low
0
0
0
0
ns
t
PHHEH
t
PHS
RP
Y
V
HH
Setup to
CE
Y
Going High
6, 8
100
100
100
100
ns
t
VPEH
t
VPS
V
PP
Setup to CE
Y
Going High
5, 8
100
100
100
100
ns
t
AVEH
t
AS
Address Setup to
CE
Y
Going High
3
50
50
50
50
ns
t
DVEH
t
DS
Data Setup to CE
Y
Going High
4
60
60
60
60
ns
t
ELEH
t
EHDX
t
DH
Data Hold from
CE
Y
High
t
CP
CE
Y
Pulse Width
50
50
60
60
ns
4
0
0
0
0
ns
t
EHAX
t
AH
Address Hold
from CE
Y
High
3
10
10
10
10
ns
t
EHWH
t
WH
WE
Y
Hold from
CE
Y
High
10
10
10
10
ns
t
EHEL
t
CPH
CE
Y
Pulse
Width High
10
20
20
20
ns
t
EHQV1
Duration of
Word/Byte
Programming
Operation
2, 5
6
6
6
6
m
s
t
EHQV2
Duration of Erase
Operation (Boot)
2, 5, 6
0.3
0.3
0.3
0.3
s
t
EHQV3
Duration of Erase
Operation
(Parameter)
2, 5
0.3
0.3
0.3
0.3
s
t
EHQV4
Duration of Erase
Operation (Main)
2, 5
0.6
0.6
0.6
0.6
s
t
QVVL
t
VPH
V
PP
Hold from
Valid SRD
5, 8
0
0
0
0
ns
t
QVPH
t
PHH
RP
Y
V
HH
Hold
from Valid SRD
6, 8
0
0
0
0
ns
t
PHBR
Boot-Block Relock
Delay
7
100
100
100
100
ns
t
IR
t
IF
Input Rise Time
10
10
10
10
ns
Input Fall Time
10
10
10
10
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE
Y
and WE
Y
in systems where
CE
Y
defines the write pulse-width (within a longer WE
Y
timing waveform), all set-up, hold and inactive WE
Y
time should
be measured relative to the CE
Y
waveform.
2, 3, 4, 5, 6, 7, 8: Refer to AC Characteristics notes for WE
Y
-Controlled Write Operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
10. See High Speed Test Configuration.
11. See Standard Test Configuration.
44
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| PA28F200BV-T80 | POWERLINE: RP40-S_D_TE - 2:1 Wide Input Voltage Range- 40 Watts Output Power- 1.6kVDC Isolation- Fixed Operating Frequency- Six-Sided Continuous Shield- Design Meet Safety Standard- Standard 76.2 x66.0x10.2mm Package- Efficiency to 90% |
| PA28F200BV-B60 | 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F200BV-B80 | 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F200BX-T60 | 2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PA28F200BVB120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F200BVB60 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F200BV-B60 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F200BVB80 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| PA28F200BV-B80 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
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