參數(shù)資料
型號(hào)： PA28F200BL-T150
廠商： INTEL CORP
元件分類： PROM
英文描述： 2-MBIT (128K x 16, 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY
中文描述： 128K X 16 FLASH 12V PROM, 150 ns, PDSO44
封裝： 1.110 X 0.525 INCH, PLASTIC, SOP-44
文件頁(yè)數(shù)： 22/48頁(yè)
文件大小： 562K
代理商： PA28F200BL-T150
28F200BX-T/B, 28F002BX-T/B
toggling either CE
Y
or OE
Y
to determine when the
program sequence is complete. Only the Read
Status Register command is valid while program-
ming is active.
When programming is complete, the status bits,
which indicate whether the program operation was
successful, should be checked. If the programming
operation was unsuccessful, Bit 4 of the status regis-
ter is set to a ‘‘1’’ to indicate a Program Failure. lf Bit
3 is set then V
PP
was not within acceptable limits,
and the WSM will not execute the programming se-
quence.
The status register should be cleared before at-
tempting the next operation. Any CUI instruction can
follow after programming is completed; however, it
must be recognized that reads from the memory,
status register, or Intelligent Identifier cannot be ac-
complished until the CUI is given the appropriate
command. A Read Array command must first be giv-
en before memory contents can be read.
Figure 12 shows a system software flowchart for de-
vice byte programming operation. Figure 13 shows a
similar flowchart for device word programming oper-
ation (28F200BX-only).
4.4.5 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CUI, along with the addresses, A
[
12:16
]
for the
28F200BX or A
[
12:17
]
for the 28F002BX, identifying
the block to be erased. These addresses are latched
internally when the Erase Confirm command is is-
sued. Block erasure results in all bits within the block
being set to ‘‘1’’.
The WSM will execute a sequence of internally
timed events to:
1. Program all bits within the block
2. Verify that all bits within the block are sufficiently
programmed
3. Erase all bits within the block and
4. Verify that all bits within the block are sufficiently
erased
While the erase sequence is executing, Bit 7 of the
status register is a ‘‘0’’.
When the status register indicates that erasure is
complete, the status bits, which indicate whether the
erase operation was successful, should be checked.
If the erasure operation was unsuccessful, Bit 5 of
the status register is set to a ‘‘1’’ to indicate an
Erase Failure. If V
PP
was not within acceptable limits
after the Erase Confirm command is issued, the
WSM will not execute an erase sequence; instead,
Bit 5 of the status register is set to a ‘‘1’’ to indicate
an Erase Failure, and Bit 3 is set to a ‘‘1’’ to identify
that V
PP
supply voltage was not within acceptable
limits.
The status register should be cleared before at-
tempting the next operation. Any CUI instruction can
follow after erasure is completed; however, it must
be recognized that reads from the memory array,
status register, or Intelligent Identifier can not be ac-
complished until the CUI is given the appropriate
command. A Read Array command must first be giv-
en before memory contents can be read.
Figure 14 shows a system software flowchart for
Block Erase operation.
4.4.5.1 Suspending and Resuming Erase
Since an erase operation typically requires 1 to 3
seconds to complete, an Erase Suspend command
is provided. This allows erase-sequence interruption
in order to read data from another block of the mem-
ory. Once the erase sequence is started, writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase se-
quence at a predetermined point in the erase algo-
rithm. The status register must be read to determine
when the erase operation has been suspended.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register operation.
Figure 15 shows a system software flowchart detail-
ing the operation.
During Erase Suspend mode, the chip can go into a
pseudo-standby mode by taking CE
Y
to V
IH
and the
active current is now a maximum of 10 mA. If the
chip is enabled while in this mode by taking CE
Y
to
V
IL
, the Erase Resume command can be issued to
resume the erase operation.
Upon completion of reads from any block other than
the block being erased, the Erase Resume com-
mand must be issued. When the Erase Resume
command is given, the WSM will continue with the
erase sequence and complete erasing the block. As
with the end of erase, the status register must be
read, cleared, and the next instruction issued in or-
der to continue.
4.4.6 EXTENDED CYCLING
Intel has designed extended cycling capability into
its ETOX III flash memory technology. The 2-Mbit
boot block flash family is designed for 100,000 pro-
gram/erase cycles on each of the five blocks. The
combination of low electric fields, clean oxide pro-
cessing and minimized oxide area per memory cell
subjected to the tunneling electric field, results in
very high cycling capability.
22
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PA28F200BV-T80 POWERLINE: RP40-S_D_TE - 2:1 Wide Input Voltage Range- 40 Watts Output Power- 1.6kVDC Isolation- Fixed Operating Frequency- Six-Sided Continuous Shield- Design Meet Safety Standard- Standard 76.2 x66.0x10.2mm Package- Efficiency to 90%
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