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Chapter 23 1024 KByte Flash Module (S12XFTM1024K5V2)
MC9S12XE-Family Reference Manual Rev. 1.07
Freescale Semiconductor
861
All assigned bits in the FERCNFG register are readable and writable.
23.3.2.7
Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
Offset Module Base + 0x0005
7
6
5
4
3
2
1
0
R
ERSERIE
PGMERIE
0
EPVIOLIE
ERSVIE1
ERSVIE0
DFDIE
SFDIE
W
Reset
0
0
0
0
0
0
0
0
Figure 23-10. Flash Error Configuration Register (FERCNFG)
Table 23-15. FERCNFG Field Descriptions
Field
Description
7
ERSERIE
EEE Erase Error Interrupt Enable
— The ERSERIE bit controls interrupt generation when a failure is detected
during an EEE erase operation.
0 ERSERIF interrupt disabled
1 An interrupt will be requested whenever the ERSERIF flag is set (see
Section 23.3.2.8
)
6
PGMERIE
EEE Program Error Interrupt Enable
— The PGMERIE bit controls interrupt generation when a failure is
detected during an EEE program operation.
0 PGMERIF interrupt disabled
1 An interrupt will be requested whenever the PGMERIF flag is set (see
Section 23.3.2.8
)
4
EPVIOLIE
EEE Protection Violation Interrupt Enable
— The EPVIOLIE bit controls interrupt generation when a
protection violation is detected during a write to the buffer RAM EEE partition.
0 EPVIOLIF interrupt disabled
1 An interrupt will be requested whenever the EPVIOLIF flag is set (see
Section 23.3.2.8
)
3
ERSVIE1
EEE Error Type 1 Interrupt Enable
— The ERSVIE1 bit controls interrupt generation when a change state error
is detected during an EEE operation.
0 ERSVIF1 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF1 flag is set (see
Section 23.3.2.8
)
2
ERSVIE0
EEE Error Type 0 Interrupt Enable
— The ERSVIE0 bit controls interrupt generation when a sector format error
is detected during an EEE operation.
0 ERSVIF0 interrupt disabled
1 An interrupt will be requested whenever the ERSVIF0 flag is set (see
Section 23.3.2.8
)
1
DFDIE
Double Bit Fault Detect Interrupt Enable
— The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see
Section 23.3.2.8
)
0
SFDIE
Single Bit Fault Detect Interrupt Enable
— The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see
Section 23.3.2.8
)