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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
MC9S12XE-Family Reference Manual , Rev. 1.07
504
Freescale Semiconductor
11.5.1
Description of Reset Operation
The reset sequence is initiated by any of the following events:
Low level is detected at the RESET pin (External Reset).
Power on is detected.
Low voltage is detected.
Illegal Address Reset is detected (see S12XMMC Block Guide for details).
COP watchdog times out.
Clock monitor failure is detected and Self-Clock Mode was disabled (SCME=0).
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles
(see
Figure 11-21
). Since entry into reset is asynchronous it does not require a running SYSCLK.
However, the internal reset circuit of the S12XECRG cannot sequence out of current reset condition
without a running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6
additional SYSCLK cycles depending on the internal synchronization latency. After 128+n SYSCLK
cycles the RESET pin is released. The reset generator of the S12XECRG waits for additional 64 SYSCLK
cycles and then samples the RESET pin to determine the originating source.
Table 11-16
shows which
vector will be fetched.
NOTE
External circuitry connected to the RESET pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic one within 64 SYSCLK cycles after the low drive is released.
COP Watchdog Reset
COPCTL (CR[2:0] nonzero)
Table 11-16. Reset Vector Selection
Sampled RESET Pin
(64 cycles after release)
Clock Monitor
Reset Pending
COP
Reset Pending
Vector Fetch
1
0
0
POR / LVR /
Illegal Address Reset/
External Reset
1
1
X
Clock Monitor Reset
1
0
1
COP Reset
0
X
X
POR / LVR /
Illegal Address Reset/ External Reset
with rise of RESET pin
Table 11-15. Reset Summary
Reset Source
Local Enable