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Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.07
472
Freescale Semiconductor
MOVW 2,X+, 2,Y+
MOVW 2,X+, 2,Y+
MOVW 2,X+, 2,Y+
CPX
#XGATE_CODE_FLASH_END
BLS
COPY_XGATE_CODE_LOOP
;###########################################
;#
START XGATE
;###########################################
MOVW #XGMCTL_ENABLE, XGMCTL
BRA
*
#
START_XGATE
;enable XGATE
;###########################################
;#
DUMMY INTERRUPT SERVICE ROUTINE
;###########################################
RTI
#
DUMMY_ISR
CPU
;###########################################
;#
XGATE DATA
;###########################################
ALIGN 1
EQU
*
EQU
*-XGATE_DATA_FLASH
DW
SCI_REGS
EQU
*-XGATE_DATA_FLASH
DB
XGATE_DATA_MSG
EQU
*-XGATE_DATA_FLASH
FCC
"Hello World!
DB
$0D
XGATE
#
XGATE_DATA_FLASH
XGATE_DATA_SCI
;pointer to SCI register space
XGATE_DATA_IDX
;string pointer
XGATE_DATA_MSG
;ASCII string
;CR
;###########################################
;#
XGATE CODE
;###########################################
ALIGN 1
LDW
R2,(R1,#XGATE_DATA_SCI)
LDB
R3,(R1,#XGATE_DATA_IDX)
LDB
R4,(R1,R3+)
STB
R3,(R1,#XGATE_DATA_IDX)
LDB
R0,(R2,#(SCISR1-SCI_REGS))
STB
R4,(R2,#(SCIDRL-SCI_REGS))
CMPL R4,#$0D
BEQ
XGATE_CODE_DONE
RTS
LDL
R4,#$00
STB
R4,(R2,#(SCICR2-SCI_REGS))
LDL
R3,#XGATE_DATA_MSG;reset R3
STB
R3,(R1,#XGATE_DATA_IDX)
RTS
EQU
(XGATE_CODE_FLASH_END-XGATE_CODE_FLASH)+XGATE_CODE_XG
#
XGATE_CODE_FLASH
;SCI -> R2
;msg -> R3
;curr. char -> R4
;R3 -> idx
;initiate SCI transmit
;initiate SCI transmit
XGATE_CODE_DONE
;disable SCI interrupts
XGATE_CODE_FLASH_END
XGATE_DUMMY_ISR_XG
10.9.3
Stack Support
TosimplifytheimplementationofaprogramstacktheXGATEcanbeconfiguredtosetRISCcoreregister
R7 to the beginning of a stack region before executing a thread. Two separate stack regions can be defined:
One for threads of priority level 7 to 4 (refer to
Section 10.3.1.5, “XGATE Initial Stack Pointer for