參數(shù)資料
型號: P89LPC9402FBD,557
廠商: NXP Semiconductors
文件頁數(shù): 37/60頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 64-LQFP
標(biāo)準(zhǔn)包裝: 450
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LCD,LED,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
其它名稱: 935288631557
P89LPC9402_1
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 22 April 2009
42 of 60
NXP Semiconductors
P89LPC9402
8-bit microcontroller with accelerated two-clock 80C51 core
7.28.5 Flash programming and erasing
Four different methods of erasing or programming of the ash are available. The ash may
be programmed or erased in the end-user application (IAP) under control of the
application’s rmware. Another option is to use the ICP mechanism. This ICP system
provides for programming through a serial clock - serial data interface. As shipped from
the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing
for the device to be programmed in circuit through the serial port. The ash may also be
programmed or erased using a commercially available EPROM programmer which
supports this device. This device does not provide for direct verication of code memory
contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire
user code space.
Remark: When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and ash
erase/program is blocked.
7.28.6 In-circuit programming
ICP is performed without removing the microcontroller from the system. The ICP facility
consists of internal hardware resources to facilitate remote programming of the
P89LPC9402 through a two-wire serial interface. Using commercially available
programmers, the NXP ICP facility has made ICP in an embedded application possible
with a minimum of additional expense in components and circuit board area. The ICP
function uses ve pins. Only a small connector needs to be available to interface your
application to a commercial programmer in order to use this feature. Additional details
may be found in the P89LPC9402
User manual.
7.28.7 In-application programming
IAP is performed in the application under the control of the microcontroller’s rmware. The
IAP facility consists of internal hardware resources to facilitate programming and erasing.
The NXP IAP has made IAP in an embedded application possible without additional
components. Two methods are available to accomplish IAP. A set of predened IAP
functions are provided in a Boot ROM and can be called through a common interface,
PGM_MTP. Several IAP calls are available for use by an application program to permit
selective erasing and programming of ash sectors, pages, security bits, conguration
bytes, and device ID. These functions are selected by setting up the microcontroller’s
registers before making a call to PGM_MTP at FF03H. The Boot ROM occupies the
program memory space at the top of the address space from FF00H to FEFFH, thereby
not conicting with the user program memory space.
In addition, IAP operations can be accomplished through the use of four SFRs consisting
of a control/status register, a data register, and two address registers. Additional details
may be found in the P89LPC9402
User manual.
7.28.8 In-system programming
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal rmware to
facilitate remote programming of the P89LPC9402 through the serial port. This rmware is
provided by NXP and embedded within each P89LPC9402 device. The NXP ISP facility
has made ISP in an embedded application possible with a minimum of additional expense
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