參數(shù)資料
型號(hào)： P89LPC9402FBD,557
廠商： NXP Semiconductors
文件頁數(shù)： 29/60頁
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 8K 64-LQFP
標(biāo)準(zhǔn)包裝： 450
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，LCD，LED，POR，PWM，WDT
輸入/輸出數(shù)： 23
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-LQFP
包裝： 托盤
其它名稱： 935288631557
P89LPC9402_1
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 22 April 2009
35 of 60
NXP Semiconductors
P89LPC9402
8-bit microcontroller with accelerated two-clock 80C51 core
7.23 Analog comparators
Two analog comparators are provided on the P89LPC9402. Input and output options allow
use of the comparators in a number of different congurations. Comparator operation is
such that the output is a logic 1 (which may be read in a register and/or routed to a pin)
when the positive input (one of two selectable pins) is greater than the negative input
(selectable from a pin or an internal reference voltage). Otherwise the output is a zero.
Each comparator may be congured to cause an interrupt when the output value changes.
The overall connections to both comparators are shown in Figure 15. The comparators
function to VDD = 2.4 V.
When each comparator is rst enabled, the comparator output and interrupt ag are not
guaranteed to be stable for 10
s. The corresponding comparator interrupt should not be
enabled during that time, and the comparator interrupt ag must be cleared before the
interrupt is enabled in order to prevent an immediate interrupt service.
7.23.1 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to as
Vref(bg), is 1.23 V ± 10 %.
7.23.2 Comparator interrupt
Each comparator has an interrupt ag contained in its conguration register. This ag is
set whenever the comparator output changes state. The ag may be polled by software or
may be used to generate an interrupt. The two comparators use one common interrupt
vector. If both comparators enable interrupts, after entering the interrupt service routine,
the user needs to read the ags to determine which comparator caused the interrupt.
7.23.3 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is
activated, but both comparators are disabled automatically in Total Power-down mode.
Fig 15. Comparator input and output connections
comparator 1
CP1
CN1
(P0.4) CIN1A
(P0.3) CIN1B
(P0.5) CMPREF
Vref(bg)
OE1
CO1
CMF1
interrupt
002aae456
CMP1 (P0.6)
EC
CMF2
comparator 2
OE2
CO2
CMP2 (P0.0)
CP2
CN2
(P0.2) CIN2A
(P0.1) CIN2B
change detect
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