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參數(shù)資料
| 型號： | P80C557E6 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single-chip 8-bit microcontroller(單片8位微控制器) |
| 中文描述： | 單芯片8位微控制器（單片8位微控制器） |
| 文件頁數(shù)： | 57/64頁 |
| 文件大?。?/td> | 476K |
| 代理商： | P80C557E6 |
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Philips Semiconductors
Product specification
P83C557E6/P80C557E6
Single-chip 8-bit microcontroller
1999 Mar 02
57
AC ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
Standard-mode
I
2
C-bus
Fast-mode
I
2
C-bus
UNIT
MIN
MAX
MIN
MAX
I
2
C Interface timing (refer to Figure 56)
f
SCL
SCL clock frequency
0
100
0
400
kHz
t
BUF
Bus free time between a STOP and START condition
4.7
–
1.3
–
μ
s
t
HD; STA
Hold time (repeated) START condition. After this period, the
first clock pulse is generated
4.0
–
0.6
–
μ
s
t
LOW
LOW period of the SCL clock
4.7
–
1.3
–
μ
s
t
HIGH
High period of the SCL clock
4.0
–
0.6
–
μ
s
t
SU; STA
Set–up time for a repeated START condition
4.7
–
0.6
–
μ
s
t
HD; DAT
Data hold time:
for CBUS competible masters (see Section 9, Notes 1, 3)
for I
2
C–bus devices
5.0
0
1
–
0
1
–
0.9
2
μ
s
t
SU; DAT
Data set–up time
250
–
100
3
–
ns
t
FD
, t
FC
Rise time of both SDA and SCL signals
–
1000
20 +
0.1C
b4
300
ns
t
FD
, t
FC
Fall time of both SDA and SCL signals
–
300
20 +
0.1C
b4
300
ns
t
SU
;
STO
Set–up time for STOP condition
4.0
–
0.6
–
μ
s
C
b
Capacitive load for each bus line
–
400
–
400
pF
t
SP
Pulse width of spikes which must be suppressed by the input
filter
All values referred to V
IH
and V
IL max
levels.
NOTES:
1. A device must internally provide a hold time of at least 300 ns from the SDA signal (referred to the V
IH min
of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
2. The maximum t
HD,DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
3. A fast–mode I
2
C–bus device can be used in a standard–mode I
2
C–bus system, but the requirement t
SU,DAT
≥
250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line t
Rmax
+ t
SU,DAT
= 1000 + 250 = 1250 ns (according to the standard–mode
I
2
C–bus specification) before the SCL line is released.
4. C
b
= total capacitance of one bus line in pF.
–
–
0
50
ns
Table 45.
External clock drive XTAL1 (refer to Figure 50)
SYMBOL
PARAMETER
VARIABLE CLOCK
f
CLK
= 3.5 to 16 MHz
UNIT
MIN
MAX
t
CLK
XTAL1 Period
63
286
ns
t
CLKH
XTAL1 HIGH time
20
–
ns
t
CLKL
XTAL1 LOW time
20
–
ns
t
CLKR
XTAL1 rise time
–
20
ns
t
CLKF
t
CYC 1)
NOTE:
1. t
CYC
= 12 f
CLK
XTAL1 fall time
–
20
ns
Controller cycle time
0.75
3.4
μ
s
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P80C557E6EBB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 8-bit microcontroller |
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| P80C557E8 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8 BIT MICROCONTROLLER |
| P80C557E8EFB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| P80C562 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller |
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