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參數(shù)資料
| 型號： | P4C187L-20LMB |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS |
| 中文描述： | 64K X 1 STANDARD SRAM, 20 ns, QCC22 |
| 封裝： | 0.290 X 0.490 INCH, LCC-22 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 323K |
| 代理商： | P4C187L-20LMB |
P4C187/187L
Page 6 of 12
Document #
SRAM111
REV B
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CE
CONTROLLED)
(9)
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Due to the ultra-high speed of the P4C187/L, care must be taken when
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the V
and ground planes
directly up to the contactor fingers. A 0.01 μF high frequency capacitor
is also required between V
CC
and ground. To avoid signal reflections,
proper termination must be used; for example, a 50
test environment
should be terminated into a 50
load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116
resistor must be used in series with
D
OUT
to match 166
(Thevenin Resistance).
AC TEST CONDITIONS
TRUTH TABLE
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
Mode
CE
WE
Output
Power
Standby
H
X
High Z
Standby
Read
L
H
D
OUT
High Z
Active
Write
L
L
Active
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