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參數(shù)資料
| 型號： | P4C1298-45PMB |
| 廠商： | Pyramid Semiconductor Corporation |
| 英文描述： | ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM |
| 中文描述： | 超高速64K的× 4靜態(tài)CMOS存儲器 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 135K |
| 代理商： | P4C1298-45PMB |
P4C1298/L
Page 5 of 11
Document #
SRAM135
REV OR
Notes:
5.
CE
is LOW and
WE
is HIGH for READ cycle.
6.
WE
is HIGH, and address must be valid prior to or coincident with
CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF READ CYCLE NO. 3 (
CE
CONTROLLED)
(5,6)
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