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參數資料
| 型號： | OZ6912 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Slot ACPI CardBus Controller |
| 中文描述： | 單槽ACPI的CardBus控制器 |
| 文件頁數： | 6/14頁 |
| 文件大?。?/td> | 140K |
| 代理商： | OZ6912 |
OZ6912
OZ6912-SF-1.5
Page 6
Pin Number
LQFP
36
Pin Name
Description
BGA
M2
Input
Type
Power
Rail
PCI_Vcc
Drive
PAR
Parity:
This pin generates PCI parity and ensures
even parity across AD[31:0] and C/BE[3:0]#.
During the address phase, PAR is valid after one
clock. With data phases, PAR is stable one clock
after a write or read transaction.
PCI Clock:
This input provides timing for all
transactions on the PCI bus to and from the
OZ6912. All PCI bus signals, except RST#, are
sampled and driven on the rising edge of
PCI_CLK. This input can be operated at
frequencies from 0 to 33 MHz.
Device Reset:
This input is used to initialize all
registers and internal logic to their reset states
and place most OZ6912 pins in a HIGH-
impedance state.
Grant
: This signal indicates that access to the bus
has been granted.
Request
: This signal indicates to the arbiter that
the OZ6912 requests use of the bus.
TTL
I/O
PCI
Spec
PCI_CLK
21
H1
-
I
PCI_Vcc
-
RST#
20
G4
-
I
AUX_Vcc
-
GNT#
2
B1
TTL
I
PCI_Vcc
PCI
Spec
PCI
Spec
REQ#
1
A1
-
TO
PCI_Vcc
Power Control and General Interface Pins
Pin Number
LQFP
59
Pin Name
Description
BGA
L8
Input
Type
Power
Rail
Aux_Vcc
Drive
RI_OUT/
PME#
Ring Indicate Out:
This pin is Ring Indicate
when the following occurs while O
Mode Control
B Register (index 2Eh) bit 7 is set to 1:
1)
Power Control (Index+02h) bit 7 set to 1
2)
Interrupt and General Control (Index+03h)
bit 7 set to 1
3)
PCI O
2
Micro Control 2 (Offset: D4h) bit X =
0
Power
Management
management event is the process by which the
OZ6912 can request a change of its power
consumption state. Usually, a PME occurs
during a request to change from a power saving
state to the fully operational state.
Speaker Output:
This output can be used to
support PC Card audio output. See O2 Mode E
Register (Index + 3Eh), bit 1.
Multifunction
Terminal
Multifunction MUX Register (Offset:08h).
Event:
A
power
-
TO
4mA
SPKR_OUT#
62
M9
TTL
I/O
Aux_Vcc
6mA
MF[6:0]
[6:0]:
See
PCI
60-61, 64-65,
67-69
K8, N9, K9,
N10, L10,
N11, M11
L11
TTL
I/O
Aux_Vcc
6mA
SUSPEND#
Suspend:
This signal is used to protect the
internal registers from clearing when the PCI
RST# signal is asserted. When low, this signal is
used to mask the PCI RESET during suspend.
This pin can be used during suspend to prevent
controller reset.
Global_Reset#:
This signal can be connected to
either PCI reset or ACPI reset depending on
system implementation. If the D3 cold state is
implemented, this signal should be connected to
the ACPI reset, otherwise, connect to PCI reset.
This signal can reset the PME content under the
D3 cold state if AUX_VCC is provided.
70
TTL
I
Aux_Vcc
-
G_RST#
66
M10
TTL
I
Aux_Vcc
-
相關PDF資料 |
PDF描述 |
|---|---|
| OZ6912B | Single-Slot ACPI CardBus Controller |
| OZ6912T | Single-Slot ACPI CardBus Controller |
| OZ6933 | ACPI CardBus Controller |
| OZ6933B | ACPI CardBus Controller |
| OZ6933T | ACPI CardBus Controller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| OZ6912B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Slot ACPI CardBus Controller |
| OZ6912T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Slot ACPI CardBus Controller |
| OZ6933 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
| OZ6933B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
| OZ6933T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ACPI CardBus Controller |
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